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ISP1760
Hi-Speed Universal Serial Bus host controller for embedded applications
Rev. 01 -- 8 November 2004 Product data sheet
1. General description
The ISP1760 is a Hi-Speed Universal Serial Bus (USB) Host Controller with a generic processor interface. It integrates one Enhanced Host Controller Interface (EHCI), one Transaction Translator (TT) and three transceivers. The Host Controller portion of the ISP1760 and the three transceivers comply to Universal Serial Bus Specification Rev. 2.0. The EHCI portion of the ISP1760 is adapted from Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0. The integrated high-performance Hi-Speed USB transceivers enable the ISP1760 to handle all Hi-Speed USB transfer speed modes: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The three downstream ports allow simultaneous connection of three devices at different speeds (high-speed, full-speed and low-speed). The generic processor interface allows the ISP1760 to be connected to various processors as a memory-mapped resource. The ISP1760 is a slave host: it does not require `bus-mastering' capabilities of the host system bus. The interface is configurable, ensuring compatibility with a variety of processors. Data transfer can be performed on 16 bits or 32 bits, using Programmed Input/Output (PIO) or Direct Memory Access (DMA) with major control signals configurable as active LOW or active HIGH. Integration of the TT allows connection to full-speed and low-speed devices, without the need of integrating Open Host Controller Interface (OHCI) or Universal Host Controller Interface (UHCI). Instead of dealing with two sets of software drivers--EHCI and OHCI or UHCI--you need to deal with only one set--EHCI--that dramatically reduces software complexity and IC cost.
2. Features
s The Host Controller portion of the ISP1760 complies with Universal Serial Bus Specification Rev. 2.0 s The EHCI portion of the ISP1760 is adapted from Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 s Contains three integrated Hi-Speed transceivers that support the high-speed, full-speed and low-speed modes s Integrates a TT for Original USB (full-speed and low-speed) device support s Up to 64-kbyte internal memory (8 k x 64 bits) accessible through a generic processor interface; operation in multitasking environments is made possible by the implementation of virtual segmentation mechanism with bank switching on task request
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
s Generic processor interface (nonmultiplexed and variable latency) with a configurable 32-bit or 16-bit external data bus; the processor interface can be defined as variable-latency or SRAM type (memory mapping) s Slave DMA support for reducing the load of the host system CPU during the data transfer to or from the memory s Integrated phase-locked loop (PLL) with a 12 MHz crystal or an external clock input s Integrated multiconfiguration FIFO s Optimized `msec-based' or `multi-msec-based' Philips Transfer Descriptor (PTD) interrupt s Tolerant I/O for low voltage CPU interface (1.65 V to 3.6 V) s 3.3 V-to-5.0 V external power supply input s Integrated 5.0 V-to-1.8 V or 3.3 V-to-1.8 V voltage regulator (internal 1.8 V for low-power core) s Internal power-on reset and low-voltage reset s Supports suspend and remote wake-up s Target current consumption: x Normal operation; one port in high-speed active: ICC < 100 mA x Suspend mode: Isusp < 150 A at the room temperature s Built-in configurable overcurrent circuitry (digital or analog overcurrent protection) s Available in LQFP128 package.
3. Applications
The ISP1760 can be used to implement a Hi-Speed USB compliant Host Controller connected to most of the CPUs present in the market today, having a generic processor interface with demultiplexed address and data bus. This is because of the efficient slave-type interface of the ISP1760. The internal architecture of the ISP1760 is such that it can be used in a large spectrum of applications requiring a high-performance internal Host Controller.
3.1 Examples of a multitude of possible applications
s s s s s s Set-top box: for connecting external high-performance mass storage devices Mobile phone: for connecting various USB devices Personal Digital Assistant (PDA): for connecting a large variety of USB devices Printer: for connecting external memory card readers, allowing direct printing Digital Still Camera (DSC): for printing to an external USB printer, for direct printing Mass storage: for connecting external memory card readers or other mass storage devices, for direct back-up. The low power consumption and deep power management modes of the ISP1760 make it particularly suitable for use in portable devices.
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Product data sheet
Rev. 01 -- 8 November 2004
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Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
4. Ordering information
Table 1: Ordering information Name ISP1760BE LQFP128 Description plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm Version SOT425-1 Type number Package
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Product data sheet
Rev. 01 -- 8 November 2004
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ISP1760
Embedded Hi-Speed USB host controller
5. Block diagram
VCC(I/O) 37 to 39, 41 to 43, 45 to 47, 49, 51, 52, 54, 56 to 58, 60 to 62, 64 to 66, 68 to 70, 72 to 74, 76 to 78, 80 DATA[15:0]/DATA[31:0] 82, 84, 86, 87, 89, 91 to 93, 95 to 98, 100 to 103, 105 A[17:1] CS_N RD_N 106 107 GENERIC PROCESSOR BUS 10, 40, 48, 59, 67, 75, 83, 94, 104, 115
ISP1760
PLL
11 12 13
XTAL1 XTAL2 CLKIN
17
WR_N 108 IRQ 112
DREQ 114 DACK 116
RISC PROCESSOR 16-bit INTERNAL MEMORY INTERFACE: 30 MHz or UP TO 64 KBYTES 60 MHz 32-bit MEMORY VIRTUAL SEGMENTATION MANAGEMENT FOR MULTITASKING SUPPORT UNIT + GLOBAL CONTROL INTERRUPT AND POWER CONTROL MANAGEMENT + MEMORY SLAVE DMA ARBITER CONTROLLER AND FIFO POWER-ON RESET + AND VBAT ON HARDWARE CONFIGURATION REGISTERS 5 V-TO-1.8 V VOLTAGE EHCI AND REGULATOR OPERATIONAL REGISTERS TRANSACTION TRANSLATOR AND RAM PIE 5 V-TO-3.3 V VOLTAGE REGULATOR
PTD AND PAYLOAD MEMORY:
122 119
RESET_N SUSPEND/ WAKEUP_N
110 5, 50, 85, 118 6, 7
VBAT_ON_N
VREG(1V8) VCC(5V0)
9
VREG(3V3)
USB FULL-SPEED AND LOW SPEED DATA PATH
USB HIGH-SPEED DATA PATH
PORT ROUTING OR CONTROL LOGIC + HOST AND HUB PORT STATUS
DIGITAL AND ANALOG OVERCURRENT DETECTION
2
REF5V
HI-SPEED USB ATX1
HI-SPEED USB ATX2
HI-SPEED USB ATX3 4, 8, 14, 17, 24, 31, 36, 44, 53, 55, 63, 71, 79, 88, 90, 99, 109, 121, 123
004aaa435
16 15
20 19 18 21 127
23 22
27 26
25 28 128
30 29 34 33 32 35 1
RREF1 GND
DP1
DM1
RREF2 OC1_N GND
DP2 GND
DM2
RREF3 OC2_N
DP3
DM3 OC3_N PSW3_N
GND
GND
GND
GND
PSW1_N
PSW2_N
Fig 1. Block diagram.
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Product data sheet
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ISP1760
Embedded Hi-Speed USB host controller
6. Pinning information
6.1 Pinning
128 103 102
1
ISP1760BE
38 39 64
65
004aaa505
Fig 2. Pin configuration (LQFP128).
6.2 Pin description
Table 2: Symbol [1] OC3_N REF5V TEST GND VREG(1V8) VCC(5V0) VCC(5V0) GND VREG(3V3) VCC(I/O) XTAL1 XTAL2 CLKIN GND
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Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Type [2] Description AI AI P P P P P AI AO I port 3 analog (5 V input) and digital overcurrent input; if not used, connect to VCC(I/O) through a 10 k resistor 5 V reference input for analog OC detector; connect a 100 nF decoupling capacitor connect to ground analog ground core power output (1.8 V); internal 1.8 V for the digital core; used for decoupling; connect a 100 nF capacitor input to internal regulators (3.0 V to 5.5 V); connect a 100 nF decoupling capacitor input to internal regulators (3.0 V to 5.5 V); connect a 100 nF decoupling capacitor oscillator ground regulator output (3.3 V); for decoupling only; connect a 100 nF capacitor and a 4.7 F to 10 F capacitor digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor 12 MHz crystal connection input; connect to ground if an external clock is used; see Table 84 12 MHz crystal connection output 12 MHz oscillator or clock input; connect to VCC(I/O) when not in use 3.3 V tolerant digital ground
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Product data sheet
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Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
Pin description...continued Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Type [2] Description AI AI/O AI/O OD AI AI/O AI/O OD AI AI/O AI/O OD I/O RREF1 ground reference resistor connection; connect a 12 k 1 % resistor between this pin and the RREF1 ground analog ground for port 1 downstream data minus port 1 analog ground downstream data plus port 1 power switch port 1, active LOW output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant RREF2 ground reference resistor connection; connect a 12 k 1 % resistor between this pin and the RREF2 ground analog ground for port 2 downstream data minus port 2 analog ground downstream data plus port 2 power switch port 2, active LOW output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant RREF3 ground reference resistor connection; connect a 12 k 1 % resistor between this pin and the RREF3 ground analog ground for port 3 downstream data minus port 3 analog ground downstream data plus port 3 power switch port 3, active LOW output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant digital ground data bit 0 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
Table 2: Symbol [1] GND RREF1 GND DM1 GND DP1 PSW1_N GND RREF2 GND DM2 GND DP2 PSW2_N GND RREF3 GND DM3 GND DP3 PSW3_N GND DATA0
DATA1
38
I/O
data bit 1 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA2
39
I/O
data bit 2 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
VCC(I/O) DATA3
40 41
P I/O
digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor data bit 3 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
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Product data sheet
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ISP1760
Embedded Hi-Speed USB host controller
Pin description...continued Pin 42 Type [2] Description I/O data bit 4 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
Table 2: Symbol [1] DATA4
DATA5
43
I/O
data bit 5 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
GND DATA6
44 45
I/O
digital ground data bit 6 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA7
46
I/O
data bit 7 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA8
47
I/O
data bit 8 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
VCC(I/O) DATA9
48 49
P I/O
digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor data bit 9 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
VREG(1V8) DATA10
50 51
P I/O
core power output (1.8 V); internal 1.8 V for the digital core; used for decoupling; connect a 100 nF capacitor data bit 10 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA11
52
I/O
data bit 11 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
GND DATA12
53 54
I/O
core ground data bit 12 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
GND DATA13
55 56
I/O
digital ground data bit 13 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA14
57
I/O
data bit 14 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA15
58
I/O
data bit 15 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
VCC(I/O)
59
P
digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor
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ISP1760
Embedded Hi-Speed USB host controller
Pin description...continued Pin 60 Type [2] Description I/O data bit 16 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
Table 2: Symbol [1] DATA16
DATA17
61
I/O
data bit 17 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA18
62
I/O
data bit 18 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
GND DATA19
63 64
I/O
digital ground data bit 19 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA20
65
I/O
data bit 20 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA21
66
I/O
data bit 21 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
VCC(I/O) DATA22
67 68
P I/O
digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor data bit 22 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA23
69
I/O
data bit 23 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA24
70
I/O
data bit 24 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
GND DATA25
71 72
I/O
digital ground data bit 25 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA26
73
I/O
data bit 26 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA27
74
I/O
data bit 27 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
VCC(I/O) DATA28
75 76
P I/O
digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor data bit 28 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
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ISP1760
Embedded Hi-Speed USB host controller
Pin description...continued Pin 77 Type [2] Description I/O data bit 29 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
Table 2: Symbol [1] DATA29
DATA30
78
I/O
data bit 30 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
GND DATA31
79 80
I/O
digital ground data bit 31 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
TEST A1 VCC(I/O) A2 VREG(1V8)
81 82 83 84 85
I P I P
connect to ground address pin 1 input, 3.3 V tolerant digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor address pin 2 input, 3.3 V tolerant core power output (1.8 V); internal 1.8 V for the digital core; used for decoupling; connect a 100 nF capacitor and a 4.7 F to 10 F capacitor address pin 3 input, 3.3 V tolerant address pin 4 input, 3.3 V tolerant core ground address pin 5 input, 3.3 V tolerant digital ground address pin 6 input, 3.3 V tolerant address pin 7 input, 3.3 V tolerant address pin 8 input, 3.3 V tolerant digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor address pin 9 input, 3.3 V tolerant address pin 10 input, 3.3 V tolerant address pin 11 input, 3.3 V tolerant address pin 12 input, 3.3 V tolerant
A3 A4 GND A5 GND A6 A7 A8 VCC(I/O) A9 A10 A11 A12
86 87 88 89 90 91 92 93 94 95 96 97 98
I I I I I I P I I I I
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ISP1760
Embedded Hi-Speed USB host controller
Pin description...continued Pin 99 100 101 102 103 104 105 106 Type [2] Description I I I I P I I digital ground address pin 13 input, 3.3 V tolerant address pin 14 input, 3.3 V tolerant address pin 15 input, 3.3 V tolerant address pin 16 input, 3.3 V tolerant digital voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor address pin 17 input, 3.3 V tolerant chip select signal that indicates the area being accessed; active LOW input, 3.3 V tolerant read enable; active LOW input, 3.3 V tolerant write enable; active LOW input, 3.3 V tolerant digital ground to indicate the presence of a minimum 3.3 V on pins 6 and 7 (open-drain); connect to VCC(I/O) through a 10 k pull-up resistor output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant not connected Host Controller interrupt signal output pad, 4 mA drive, 3.3 V tolerant not connected DMAC request for the Host Controller output pad, 4 mA drive, 3.3 V tolerant digital voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor Host Controller DMA request acknowledgment; when not in use, connect to VCC(I/O) through a 10 k pull-up resistor input, 3.3 V tolerant connect to ground core power output (1.8 V); internal 1.8 V for the digital core; used for decoupling; connect a 100 nF capacitor Host Controller suspend and wake-up; three-state suspend output (active LOW) and wake-up input circuits are connected together
Table 2: Symbol [1] GND A13 A14 A15 A16 VCC(I/O) A17 CS_N
RD_N WR_N GND VBAT_ON_N
107 108 109 110
I I OD
n.c. IRQ n.c. DREQ VCC(I/O) DACK
111 112 113 114 115 116
O O P I
TEST VREG(1V8)
117 118
P I/OD
SUSPEND/ 119 WAKEUP_ N
* *
HIGH = output is three-state; ISP1760 is in suspend mode; connect to VCC(I/O) through an external 10 k pull-up resistor LOW = output is LOW; ISP1760 is not in suspend mode.
output pad, open-drain, 4 mA output drive, 3.3 V tolerant
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ISP1760
Embedded Hi-Speed USB host controller
Pin description...continued Pin 120 121 122 123 124 125 126 127 128 Type [2] Description I AI AI pull up to VCC(I/O) core ground external power-up reset; active LOW input, 3.3 V tolerant analog ground connect a 220 nF capacitor between this pin and pin 125 connect a 220 nF capacitor between this pin and pin 124 connect to 3.3 V port 1 analog (5 V input) and digital overcurrent input; if not used, connect to VCC(I/O) through a 10 k resistor port 2 analog (5 V input) and digital overcurrent input; if not used, connect to VCC(I/O) through a 10 k resistor
Table 2: Symbol [1] TEST GND RESET_N GND TEST TEST TEST OC1_N OC2_N
[1] [2]
Symbol names ending with underscore N (for example, NAME_N) represent active LOW signals. I = input only; O = output only; I/O = digital input/output; OD = open-drain output; AI/O = analog input/output; AI = analog input; P = power.
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ISP1760
Embedded Hi-Speed USB host controller
7. Functional description
7.1 ISP1760 internal architecture: Advanced Philips Slave Host Controller and hub
The EHCI block and the Hi-Speed USB hub block are the main components of the Advanced Philips Slave Host Controller. The EHCI is the latest generation design, with improved data bandwidth. The EHCI in the ISP1760 is adapted from Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0. The internal Hi-Speed USB hub block replaces the companion Host Controller block used in the original PCI Hi-Speed USB Host Controllers to handle the full-speed and low-speed modes. The hardware architecture in the ISP1760 is simplified to help reduce cost and development time, by eliminating the additional work involved in implementing the OHCI software required to support the full-speed and low-speed modes. Figure 3 shows the internal architecture of the ISP1760. The ISP1760 implements the EHCI that has an internal port--the Root Hub port (not available externally)--on which the internal hub is connected. The three external ports are always routed to the internal hub. The internal hub is a Hi-Speed USB (USB 2.0) hub including the TT. Remark: The root hub must be enabled and the internal hub must be enumerated. Enumerate the internal hub as if it is externally connected. For details, refer to ISP176x Linux Programming Guide (AN10042). At the Host Controller reset and initialization, the internal Root Hub port will be polled until a new connection is detected, showing the connection of the internal hub. The internal Hi-Speed USB hub is enumerated using a sequence similar to a standard Hi-Speed USB hub enumeration sequence, and the polling on the Root Hub is stopped because the internal Hi-Speed USB hub will never be disconnected. When enumerated, the internal hub will report the three externally available ports.
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Embedded Hi-Speed USB host controller
EHCI ROOT HUB PORTSC1
ENUMERATION AND POLLING USING ACTUAL PTDs
INTERNAL HUB (TT)
PORT1
PORT2
PORT3
EXTERNAL PORTS
004aaa513
Fig 3. Internal hub.
7.2 Host Controller buffer memory block
7.2.1 General considerations
The internal addressable Host Controller buffer memory is 63 kbytes. The 63-kbyte effective memory size is the result of subtracting the size of registers (1 kbyte) from the total addressable memory space defined in the ISP1760 (64 kbytes). This is the optimized value for achieving the highest performance with a minimal cost. The ISP1760 is a slave Host Controller. This means that it does not need access to the local bus of the system to transfer data from the memory of the system to the ISP1760 internal memory, unlike the case of the original PCI Hi-Speed USB Host Controllers. Therefore, correct data must be transferred to both the Philips Transfer Descriptor (PTD) area and the payload area by Parallel I/O (PIO) (CPU access) or programmed DMA. The `slave-host' architecture ensures better compatibility with most of the processors present in the market today because not all processors allow a `bus-master' on the local bus. It also allows better load balancing of the processor's local bus because only the internal bus arbiter of the processor controls the transfer of data dedicated to USB. This prevents the local bus from being busy when other more important transfers may be in the queue; and therefore achieving a `linear' system data flow that has less impact on other processes running at the same time. The considerations mentioned are also the main reason for implementing the prefetching technique, instead of using a READY signal. The resulting architecture avoids `freezing' of the local bus (by asserting READY), enhancing the ISP1760 memory access time, and avoiding introduction of programmed additional wait states. For details, see Section 7.3 and Section 8.3.8.
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ISP1760
Embedded Hi-Speed USB host controller
The total amount of memory allocated to the payload determines the maximum transfer size specified by a PTD--a larger internal memory size results in less CPU interruption for transfer programming. This means less time spent in context switching, resulting in better CPU usage. A larger buffer also implies a larger amount of data can be transferred. The transfer, however, can be done over a longer period of time, to maintain the overall system performance. Each transfer of the USB data on the USB bus can span for up to a few milliseconds before requiring further CPU intervention for data movement. The internal architecture of the ISP1760 allows a flexible definition of the memory buffer for optimization of the data transfer on the CPU extension bus and the USB. It is possible to implement various data transfer schemes, depending on the number and type of USB devices present (for example: push-pull--data can be written to half of the memory while data in the other half is being accessed by the Host Controller and sent on the USB bus). This is useful especially when a high-bandwidth `continuous or periodic' data flow is required. Through an analysis of the hardware and software environment regarding the usual data flow and performance requirements of most embedded systems, Philips has determined the optimal size for the internal buffer as approximately 64 kbytes.
7.2.2 Structure of the ISP1760 Host Controller memory
The 63-kbyte internal memory consists of the PTD area and the payload area. Both the PTD and payload memory zones are divided into three dedicated areas for each main type of USB transfer: isochronous (ISO), interrupt (INT) and Acknowledged Transfer List (ATL). As shown in Table 3, the PTD areas for ISO, INT and ATL are grouped at the beginning of the memory, occupying the address range 0400h to 0FFFh, following the address space of the registers. The payload or data area occupies the next memory address range 1000h to FFFFh, meaning that 60 kbytes of memory are allocated for the payload data. A maximum of 32 PTD areas and their allocated payload areas can be defined for each type of transfer. The structure of a PTD is similar for every transfer type and consists of eight Double Words (DWs) that must be correctly programmed for a correct USB data transfer. The reserved bits of a PTD must be set to logic 0. A detailed description of the PTD structure can be found in Section 9. The transfer size specified by the PTD determines the contiguous USB data transfer that can be performed without any CPU intervention. The respective payload memory area must be equal to the transfer size defined. The maximum transfer size is flexible and can be optimized, depending on the number and nature of USB devices or PTDs defined and their respective MaxPacketSize. The CPU will program the DMA to transfer the necessary data in the payload memory. The next CPU intervention will be required only when the current transfer is completed and DMA programming is necessary to transfer the next data payload. This is normally signaled by the IRQ that is generated by the ISP1760 on completing the current PTD, meaning all the data in the payload area was sent on the USB bus. The external IRQ signal is asserted according to the settings in the IRQ Mask OR or IRQ Mask AND registers, see Section 8.4.
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ISP1760
Embedded Hi-Speed USB host controller
The RAM is structured in blocks of PTDs and payloads so that while the USB is executing on an active transfer-based PTD, the processor can simultaneously fill up another block area in the RAM. A PTD and its payload can then be updated on-the-fly without stopping or delaying any other USB transaction or corrupting the RAM data. Some of the design features are:
* The address range of the internal RAM buffer is from 0400h to FFFFh. * The internal memory contains isochronous, interrupt and asynchronous PTDs, and
respective defined payloads.
* All accesses to the internal memory are double-word aligned. * Internal memory address range calculation:
Memory address = (CPU address - 0400h) (shift right >> 3). Base address is 0400h.
Table 3: ISO INT ATL Payload Memory address CPU address 0400h to 07FFh 0800h to 0BFFh 0C00h to 0FFFh 1000h to FFFFh Memory address 0000h to 007Fh 0080h to 00FFh 0100h to 017Fh 0180h to 1FFFh
Memory map
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63 kbytes
PTD1 PTD2 ISOCHRONOUS .. PTD32 PTD1 PTD2 .. INTERRUPT PTD32 PTD1 PTD2 .. REGISTERS ASYNC PTD32 PAYLOAD D[15:0]/D[31:0] ........
USB BUS
USB HIGH-SPEED HOST AND TRANSACTION TRANSLATOR (FULL-SPEED AND LOW-SPEED)
PAYLOAD
PAYLOAD address data (64 bits)
240 MB/s
MEMORY MAPPED INPUT/OUTPUT, MEMORY MANAGEMENT UNIT, SLAVE DMA CONTROLLER AND INTERRUPT CONTROL
A[17:1] CS_N RD_N WR_N IRQ DREQ MICROPROCESSOR
ARBITER
DACK
control signals
004aaa436
Fig 4. Memory segmentation and access block diagram.
Both the CPU interface logic and the USB Host Controller require access to the internal ISP1760 RAM at the same time. The internal arbiter controls these accesses to the internal memory, organized internally on a 64-bit data bus width, allowing a maximum bandwidth of 240 MB/s. This bandwidth avoids any bottleneck on accesses both from the CPU interface and the internal USB Host Controller.
7.3 Accessing the ISP1760 Host Controller memory: PIO and DMA
The CPU interface of the ISP1760 can be configured for a 16-bit or 32-bit data bus width. When the ISP1760 is configured for a 16-bit data bus width, the upper unused 16 data lines must be pulled up to VCC(I/O). This can be achieved by connecting DATA[31:16] lines together to a single 10 k pull-up resistor. The 16-bit or 32-bit data bus width configuration is done by programming bit 8 of the HW Mode Control register. This will determine the register and memory access types in both PIO and DMA modes to all internal blocks: Host Controller, Peripheral Controller and OTG Controller. All accesses must be word-aligned for 16-bit mode and double-word aligned for 32-bit mode, where one word = 16 bits. When accessing the Host Controller registers in 16-bit mode, the
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register access must always be completed using two subsequent accesses. In the case of a DMA transfer, the 16-bit or 32-bit data bus width configuration will determine the number of bursts that will complete a certain transfer length. In PIO mode, CS_N, WR_N and RD_N are used to access registers and memory. In DMA mode, the data validation is performed by DACK--instead of CS_N--together with the WR_N and RD_N signals. The DREQ signal will always be asserted as soon as the ISP1760 DMA is enabled, as described in the following section.
7.3.1 PIO mode access--memory read cycle
The following method has been implemented to reduce the read access timing in the case of a memory read:
* The Memory register contains the starting address and the bank selection to read
from the memory. Before every new read cycle of the same or different banks, an appropriate value is written to this register.
* Once a value is written to this register, the address is stored in the FIFO of that bank
and is then used to prefetch data for the memory read of that bank. For every subsequent read operation executed at a contiguous address, the address pointer corresponding to that bank is automatically incremented to prefetch the next data to be sent to the CPU. Memory read accesses for multiple banks can be interleaved. In this case, the FIFO block handles the MUXing of appropriate data to the CPU.
* The address written to the Memory register is incremented and used to successively
prefetch data from the memory irrespective of the value on the address bus for each bank, until a new value for a bank is written to the Memory register. For example, consider the following sequence of operations: - Write the starting (read) address 4000h and bank1 = 01 to the Memory register. When RD_N is asserted for three cycles with A[17:16] = 01, the returned data corresponds to addresses 4000h, 4004h and 4008h. Remark: Once 4000h is written to the Memory register for bank1, the bank select value determines the successive incremental addresses used to fetch the data. That is, the fetching of data is independent of the address on A[15:0] lines. - Write the starting (read) address 4100h and bank2 = 10 to the Memory register. When RD_N is asserted for four cycles with A[17:16] = 10, the returned data corresponds to addresses 4100h, 4104h, 4108h and 410Ch. Consequently, the RD_N assertion with A[17:16] = 01 will return data from 400Ch because the bank1 read stopped there in the previous cycle. Also, RD_N assertions with A[17:16] = 010 will now return data from 4110h because the bank2 read stopped there in the previous cycle.
7.3.2 PIO mode access--memory write cycle
The PIO memory write access is similar to a normal memory access. It is not necessary to set the prefetching address before a write cycle to the memory. The ISP1760 internal write address will not be automatically incremented during consecutive write accesses, unlike in a series of ISP1760 memory read cycles. The memory write address must be incremented before every access.
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7.3.3 PIO mode access--register read cycle
The PIO register read access is similar to a general register access. It is not necessary to set a prefetching address before a register read. The ISP1760 register read address will not be automatically incremented during consecutive read accesses, unlike in a series of ISP1760 memory read cycles. The ISP1760 register read address must be correctly specified before every access.
7.3.4 PIO mode access--register write cycle
The PIO register write access is similar to a general register access. It is not necessary to set a prefetching address before a register write. The ISP1760 register write address will not be automatically incremented during consecutive write accesses, unlike in a series of ISP1760 memory read cycles. The ISP1760 register write address must be correctly specified before every access.
7.3.5 DMA--read and write operations
The internal ISP1760 Host Controller DMA is a slave DMA. The host system processor or DMA must ensure the data transfer to or from the ISP1760 memory. The ISP1760 DMA supports a DMA burst length of 1, 4, 8 and 16 cycles for both the 16-bit and 32-bit data bus width. DREQ will be asserted at the beginning of the first burst of a DMA transfer and will be deasserted on the last cycle (RD_N or WR_N active pulse) of that burst. It will be reasserted shortly after the DACK deassertion, as long as the DMA transfer counter was not reached. DREQ will be deasserted on the last cycle when the DMA transfer counter is reached and will not reasserted until the DMA reprogramming is performed. Both the DREQ and DACK signals are programmable as active LOW or active HIGH, according to the system requirements. The DMA start address must be initialized in the respective register, and the subsequent transfers will automatically increment the internal ISP1760 memory address. A register or memory access or access to other system memory can occur in between DMA bursts, whenever the bus is released because DACK is deasserted, without affecting the DMA transfer counter or the current address. Any memory area can be accessed by the system's DMA at any starting address because there are no predefined memory blocks. The DMA transfer must start on a word or Double Word address, depending on whether the data bus width is set to 16 bit or 32 bit. DMA is the most efficient method to initialize the payload area, to reduce the CPU usage and overall system loading. The ISP1760 does not implement EOT to signal the end of a DMA transfer. If programmed, an interrupt may be generated by the ISP1760 at the end of the DMA transfer. The slave DMA of the ISP1760 will issue a DREQ to the DMA controller of the system to indicate that it is programmed for transfer and data is ready. The system DMA controller may also start a transfer without the need of the DREQ, if the ISP1760 memory is available for the data transfer and the ISP1760 DMA programming is completed.
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It is also possible that the system's DMA will perform a memory-to-memory type of transfer between the system memory and the ISP1760 memory. The ISP1760 will be accessed in the PIO mode. Consequently, memory read operations must be preceded by initializing the Memory register (address 033Ch), as described in Section 7.3.1. No IRQ will be generated by the ISP1760 on completing the DMA transfer but an internal processor interrupt may be generated to signal that the DMA transfer is completed. This is mainly useful in implementing the double-buffering scheme for data transfer to optimize the USB bandwidth. The ISP1760 DMA programming involves:
* Set the active levels of signals DREQ and DACK in the HW Mode Control register. * The DMA Start Address register contains the first memory address at which the data
transfer will start. It must be word-aligned in the 16-bit data bus mode and double word aligned in the 32-bit data bus mode.
* The programming of the DMA Configuration register specifies:
- The type of transfer that will be performed: read or write - The burst size--expressed in bytes--is specified, regardless of the data bus width. For the same burst size, a double number of cycles will be generated in the 16-bit mode data bus width as compared to the 32-bit mode. - The transfer length--expressed in number of bytes--defines the number of bursts. The DREQ will be deasserted and asserted to generate the next burst, as long as there are bytes to be transferred. At the end of a transfer, the DREQ will be deasserted and an IRQ can be generated if DMAEOTINT (bit 3 in the Interrupt register) is set. The maximum DMA transfer size is equal to the maximum memory size. The transfer size can be an odd or even number of bytes, as required. If the transfer size is an odd number of bytes, the number of bytes transferred by the system's DMA is equal to the next multiple of two for the 16-bit data bus width or four for the 32-bit data bus width. For a write operation, however, only the specified odd number of bytes in the ISP1760 memory will be affected. - Enable ENABLE_DMA (bit 1) of the DMA Configuration register to determine the assertion of DREQ immediately after setting the bit. After programming the preceding parameters, the system's DMA may be enabled (waiting for the DREQ to start the transfer or immediate transfer may be started). The programming of the system's DMA must match the ISP1760 DMA parameters programmed above. Only one DMA transfer may take place at a time. A PIO mode data transfer may occur simultaneously with a DMA data transfer, in the same or a different memory area.
7.4 Interrupts
The ISP1760 will assert an IRQ according to the source or event in the Interrupt register. The main steps to enable the IRQ assertion are: 1. Set GLOBAL_INTR_EN (bit 0) in the HW Mode Control register. 2. Define the IRQ active as level or edge in INTR_LEVEL (bit 1) of the HW Mode Control register.
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3. Define the IRQ polarity as active LOW or active HIGH in INTR_POL (bit 2) of the HW Mode Control register. These settings must match the IRQ settings of the host processor. By default, interrupt is level-triggered and active LOW. 4. Program the individual interrupt enable bits in the Interrupt Enable register. The software will need to clear the interrupt status bits in the Interrupt register before enabling individual interrupt enable bits. Additional IRQ characteristics can be adjusted in the Edge Interrupt Count register, as necessary, applicable only when IRQ is set to be edge-active (a pulse of a defined width is generated every time IRQ is active). Bits 15 to 0 of the Edge Interrupt Count register define the IRQ pulse width. The maximum pulse width that can be programmed is FFFFh, corresponding to a 1 ms pulse width. This setting is necessary for certain processors that may require a different minimum IRQ pulse width than the default value. The default IRQ pulse width set at power on is approximately 500 ns. Bits 31 to 24 of the Edge Interrupt Count register define the minimum interval between two interrupts to avoid frequent interrupts to the CPU. The default value of 00h attributed to these bits determines the normal IRQ generation, without any delay. When a delay is programmed and the IRQ becomes active after the respective delay, several IRQ events may have already occurred. All the interrupt events are represented by the respective bits allocated in the Interrupt register. There is no mechanism to show the order or the moment of occurrence of an interrupt. The asserted bits in the Interrupt register can be cleared by writing back the same value to the Interrupt register. This means that writing logic 1 to each of the set bits will reset the corresponding bits to the initial inactive state. The IRQ generation rules that apply according to the preceding settings are:
* If an event of interrupt occurs but the respective bit in the Interrupt Enable register is
not set, then the respective Interrupt register bit is set but the interrupt signal is not asserted. An interrupt will be generated when interrupt is enabled and the respective bit in the Interrupt Enable register is set.
* For a level trigger, an interrupt signal remains asserted until the processor clears the
Interrupt register by writing logic 1 to clear the Interrupt register bits that are set.
* If an interrupt is made edge-sensitive and is asserted, writing to clear the Interrupt
register will not have any effect because the interrupt will be asserted for a prescribed amount of clock cycles.
* The clock stopping mechanism does not affect the generation of an interrupt. This is
useful during the suspend and resume cycles, when an interrupt is generated to signal a wake-up event. The IRQ generation can also be conditioned by programming the IRQ Mask OR and IRQ Mask AND registers. Setting some of the bits in these registers to logic 1 will determine the IRQ generation only when the respective AND or OR conditions of completing the respective PTDs is met.
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With the help of the IRQ Mask AND and IRQ Mask OR registers for each type of transfer--ISO, INT and bulk--software can determine which PTDs get priority and an interrupt will be generated when the AND or OR conditions are met. The PTDs that are set will wait until the respective bits of the remaining PTDs are set and then all PTDs generate an interrupt request to the CPU together. The registers definition shows that the AND or OR conditions are applicable to the same category of PTDs--ISO, INT, ATL. When an IRQ is generated, the PTD Done Map registers and the respective V bits will show which PTDs were completed. The rules that apply to the IRQ Mask AND or IRQ Mask OR settings are:
* The OR mask has a higher priority over the AND mask. An IRQ is generated if bit n of
the done map is set and the corresponding bit n of the OR Mask register is set.
* If the OR mask for any done bit is not set, then the AND mask comes into picture. An
IRQ is generated if all the corresponding done bits of the AND Mask register are set. For example: If bits 2, 4 and 10 are set in the AND Mask register, an IRQ is generated only if bits 2, 4, 10 of the done map are set.
* If using the IRQ interval setting for the bulk PTD, an interrupt will only occur at the
regular time interval as programmed in the ATL Done Timeout register. Even if an interrupt event occurs before the timeout of the register, no IRQ will be generated until the time is up. For an example on using the IRQ Mask AND or IRQ Mask OR registers without the ATL Done Timeout register, see Table 4. The AND function: Activate the IRQ only if PTDs 1, 2 and 4 are done. The OR function: If any of the PTDs 7, 8 or 9 are done, an IRQ for each of the PTD will be raised.
Table 4: PTD 1 2 3 4 5 6 7 8 9 1 1 0 1 0 0 0 0 0 Using the IRQ Mask AND or IRQ Mask OR registers AND register OR register 0 0 0 0 0 0 1 1 1 Time 1 ms 3 ms 5 ms 6 ms 7 ms PTD done 1 1 1 1 1 1 IRQ active because of AND active because of OR active because of OR active because of OR
7.5 Phase-Locked Loop (PLL) clock multiplier
The internal PLL requires a 12 MHz input, which can be a 12 MHz crystal or a 12 MHz clock already existing in the system with a precision better than 50 ppm. This allows the use of a low-cost 12 MHz crystal that also minimizes Electro-Magnetic Interference (EMI). When an external crystal is used, make sure the CLKIN pin is connected to VCC(I/O).
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The PLL block generates all the main internal clocks required for normal functionality of various blocks: 30 MHz, 48 MHz and 60 MHz. No external components are required for the PLL operation.
7.6 Power management
The ISP1760 implements a flexible power management scheme, allowing various power saving stages. The usual powering scheme implies programming EHCI registers and the internal Hi-Speed USB (USB 2.0) hub in the same way it is done in the case of a PCI Hi-Speed USB Host Controller with a Hi-Speed USB hub attached. When the ISP1760 is in suspend mode, the main internal clocks will be stopped to ensure minimum power consumption. An internal LazyClock of 100 kHz 40 % will continue running. This allows initiating a resume on one of the following events:
* External USB device connect or disconnect * Assertion of the CS_N signal because of any access to the ISP1760 * Driving the SUSPEND/WAKEUP_N pin to a LOW level.
The SUSPEND/WAKEUP_N pin is a bidirectional pin. This pin should be connected to one of the GPIO pins of a processor. The awake state can be verified by reading the LOW level of this pin. If the level is HIGH, it means that the ISP1760 is in the suspend state. The SUSPEND/WAKEUP_N pin requires a pull-up because in the ISP1760 suspended state the pin becomes three-state and can be pulled down, driving it externally by switching the processor's GPIO line to the output mode to generate the ISP1760 wake-up. The SUSPEND/WAKEUP_N pin is a three-state output. It is also an input to the internal wake-up logic. When in suspend mode, the ISP1760 internal wake-up circuitry will sense the status of the SUSPEND/WAKEUP_N pin:
* If it remains pulled-up, no wake-up is generated because a HIGH is sensed by the
internal wake-up circuit.
* If the pin is externally pulled LOW (for example, by the GPIO line or just as a test by
jumper), the input to the wake-up circuitry becomes LOW and the wake-up is internally initiated. The resume state has a clock-off count timer defined by bits 31 to 16 of the Power Down Control register. The default value of this timer is 10 ms, meaning that the resume state will be maintained for 10 ms. If during this time, the RUN/STOP bit in the USBCMD register is set to logic 1, the Host Controller will go into a permanent resume--the normal functional state. If the RUN/STOP bit is not set during the time determined by the clock-off count, the ISP1760 will switch back to suspend mode after the specified time. The maximum delay that can be programmed in the clock-off count field is approximately 500 ms.
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Additionally, the Power Down Control register allows the ISP1760 internal blocks to be disabled for lower power consumption as defined in Table 5. The lowest suspend current that can be achieved is approximately 100 A at room temperature. The suspend current will increase with the increase in temperature, with approximately 300 A at 40 C and up to a typical 1 mA at 85 C. The system is not in suspend mode when its temperature increases above 40 C. Therefore, even a 1 mA current consumption by the ISP1760 (in suspend mode) can be considered negligible. In normal environmental conditions, when the system is in suspend mode, the maximum ISP1760 temperature will be approximately 40 C (determined by the ambient temperature) so the ISP1760 maximum suspend current will be below 300 A. An alternative solution to achieve a very low suspend current is to completely switch off the VCC(5V0) power input by using an external PMOS transistor, controlled by one of the GPIO pins of the processor. This is possible because the ISP1760 can be used in the hybrid mode, which allows only the VCC(I/O) powered on to avoid loading of the system bus. The time from wake-up to suspend will be approximately 100 ms when the ISP1760 power is always on. It is necessary to wait for the CLK_RDY interrupt assertion before programming the ISP1760 because internal clocks are stopped during deep-sleep suspend and restarted after the first wake-up event. The occurrence of the CLK_RDY interrupt means that the internal clocks are running and the normal functionality is achieved. It is estimated that the CLK_RDY interrupt will be generated less than 100 s after the wake-up event, if the power to the ISP1760 was on during suspend. If the ISP1760 is used in the hybrid mode and VCC(5V0) is off during suspend, a 2 ms reset pulse is required when the power is switched back to on, before starting to program the resume state. This will ensure that the internal clocks are running and all logics reach a stable initial state.
7.7 Overcurrent detection
The ISP1760 can implement a digital or analog overcurrent detection scheme. Bit 15 of the HW Mode Control register can be programmed to select the analog or digital overcurrent detection. An analog overcurrent detection circuit is integrated on-chip. The main features of this circuit are self reporting, automatic resetting, low-trip time and low cost. This circuit offers an easy solution at no extra hardware cost on the board. The port power will be automatically disabled by the ISP1760 on an overcurrent event occurrence, by deasserting the PSWn_N signal without any software intervention. When using the integrated analog overcurrent detection, the range of the overcurrent detection voltage for the ISP1760 is 45 mV to 100 mV. Calculation of the external components should be based on the 45 mV value, with the actual overcurrent detection threshold usually positioned in the middle of the interval. For an overcurrent limit of 500 mA per port, a PMOS with RDSON of approximately 100 m is required. If a PMOS with a lower RDSON is used, analog overcurrent detection can be adjusted using a series resistor; see Figure 5. VPMOS = VTRIP = VTRIP(intrinsic) - (IOC(nom) x Rtd), where: VPMOS = voltage drop on PMOS
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IOC(nom) = 1 A.
5V
IOC Rtd(1) REF5V PSWn_N OCn_N
ISP1760
004aaa662
(1) Rtd is optional.
Fig 5. Adjusting analog overcurrent detection limit (optional).
The digital overcurrent scheme requires using an external power switch with integrated overcurrent detection, such as: LM3526, MIC2526 (2 ports) or LM3544 (4 ports). These devices are controlled by PSWn_N signals corresponding to each port. In the case of overcurrent occurrence, these devices will assert OCn_N signals. On OCn_N assertion, the ISP1760 cuts off the port power by deasserting PSWn_N. The external integrated power switch will also automatically cut-off the port power in the case of an overcurrent event, by implementing thermal shutdown. An internal delay filter of 1 ms to 3 ms will prevent false overcurrent reporting because of in-rush currents when plugging a USB device.
7.8 Power supply
Figure 6 shows the ISP1760 power supply connection.
ISP1760
6, 7 10, 40, 48, 59, 67, 75, 83, 94, 104, 115 85
10 F 100 nF
VCC(5V0)
3.3 V to 5 V
100 nF
VCC(I/O)
1.65 V to 3.6 V
100 nF
VREG(1V8)
VREG(1V8) 5, 50, 118
100 nF
VREG(3V3) 9
10 F 100 nF
004aaa533
Fig 6. ISP1760 power supply connection.
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Figure 7 shows the most commonly used power supply connection.
ISP1760
6, 7, 10, 40, 48, 59, 67, 75, 83, 94, 104, 115 VCC(5V0), VCC(I/O) 3.3 V
100 nF
VREG(1V8) 85
10 F 100 nF
VREG(1V8) 5, 50, 118
100 nF
VREG(3V3) 9
10 F 100 nF
004aaa534
Fig 7. Most commonly used power supply connection.
7.9 Power-on reset (POR)
When VCC(5V0) is directly connected to the RESET_N pin, the internal POR pulse width (tPORP) will be typically 800 ns. The pulse is started when VCC(5V0) rises above VTRIP (1.2 V). To give a better view of the functionality, Figure 8 shows a possible curve of VCC(5V0) with dips at t2-t3 and t4-t5. If the dip at t4-t5 is too short (that is, < 11 s), the internal POR pulse will not react and will remain LOW. The internal POR starts with a 1 at t0. At t1, the detector will see the passing of the trip level and a delay element will add another tPORP before it drops to 0. The internal POR pulse will be generated whenever VCC(5V0) drops below VTRIP for more than 11 s.
VCC(5V0) VTRIP
t0
t1 tPORP
t2
t3 tPORP
t4
t5 PORP(1)
004aaa584
(1) PORP = power-on reset pulse.
Fig 8. Internal power-on reset timing.
The RESET_N pin can be either connected to VCC(I/O) (using the internal POR circuit) or externally controlled (by the microcontroller, ASIC, and so on). Figure 9 shows the availability of the clock with respect to the external POR.
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RESET_N EXTERNAL CLOCK
004aaa583
A
Stable external clock is available at A.
Fig 9. Clock with respect to the external power-on reset.
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8. Registers
Table 5 shows the bit description of the registers.
* All registers range from 0000h to 03FFh. These registers can be read or written as
double word, that is 32-bit data. In the case of a 16-bit data bus width, two subsequent accesses are necessary to complete the register read or write cycle.
* Operational registers range from 0000h to 01FFh. Configuration registers range from
0300h to 03FFh.
Table 5: Address 0000h 0002h 0004h 0008h 0020h 0024h 0028h 002Ch 0030h 0060h 0064h 0130h 0134h 0138h 0140h 0144h 0148h 0150h 0154h 0158h 0200h-02FFh 0300h 0304h 0308h 030Ch 0330h 0334h 0338h 033Ch Register overview Register CAPLENGTH HCIVERSION HCSPARAMS HCCPARAMS USBCMD USBSTS USBINTR FRINDEX CTRLDSSEGMENT CONFIGFLAG PORTSC1 ISO PTD Done Map ISO PTD Skip Map ISO PTD Last PTD INT PTD Done Map INT PTD Skip Map INT PTD Last PTD ATL PTD Done Map ATL PTD Skip Map ATL PTD Last PTD reserved HW Mode Control Chip ID Scratch SW Reset DMA Configuration Buffer Status ATL Done Timeout Memory Reset value 20h 0100h 0000 0011h 0000 0086h 0008 0000h 0000 1000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 2000h 0000 0000h FFFF FFFFh 0000 0000h 0000 0000h FFFF FFFFh 0000 0000h 0000 0000h FFFF FFFFh 0000 0000h 0000 0000h 0001 1761h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h References Section 8.1.1 on page 28 Section 8.1.2 on page 28 Section 8.1.3 on page 28 Section 8.1.4 on page 29 Section 8.2.1 on page 30 Section 8.2.2 on page 31 Section 8.2.3 on page 32 Section 8.2.4 on page 33 Section 8.2.5 on page 34 Section 8.2.6 on page 34 Section 8.2.7 on page 35 Section 8.2.8 on page 36 Section 8.2.9 on page 37 Section 8.2.10 on page 37 Section 8.2.11 on page 37 Section 8.2.12 on page 38 Section 8.2.13 on page 38 Section 8.2.14 on page 38 Section 8.2.15 on page 38 Section 8.2.16 on page 39 Section 8.3.1 on page 39 Section 8.3.2 on page 41 Section 8.3.3 on page 41 Section 8.3.4 on page 41 Section 8.3.5 on page 42 Section 8.3.6 on page 43 Section 8.3.7 on page 44 Section 8.3.8 on page 44
EHCI capability registers
EHCI operational registers
Configuration registers
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Register overview...continued Register Edge Interrupt Count DMA Start Address Power Down Control Port 1 Control Interrupt Interrupt Enable ISO IRQ Mask OR INT IRQ Mask OR ATL IRQ Mask OR ISO IRQ Mask AND INT IRQ Mask AND ATL IRQ Mask AND Reset value 0000 000Fh 0000 0000h 03E8 1BA0h 0086 0086h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h References Section 8.3.9 on page 45 Section 8.3.10 on page 46 Section 8.3.11 on page 46 Section 8.3.12 on page 48 Section 8.4.1 on page 50 Section 8.4.2 on page 51 Section 8.4.3 on page 53 Section 8.4.4 on page 53 Section 8.4.5 on page 53 Section 8.4.6 on page 54 Section 8.4.7 on page 54 Section 8.4.8 on page 54
Table 5: Address 0340h 0344h 0354h 0374h 0310h 0314h 0318h 031Ch 0320h 0324h 0328h 032Ch
Interrupt registers
8.1 EHCI capability registers
8.1.1 CAPLENGTH register (R: 0000h)
The bit description of the Capability Length (CAPLENGTH) register is given in Table 6.
Table 6: Bit 7 to 0 CAPLENGTH register: bit description Symbol CAPLENGTH [7:0] Access R Value 20h Description Capability Length: This is used as an offset. It is added to the register base to find the beginning of the operational register space.
8.1.2 HCIVERSION register (R: 0002h)
Table 7 shows the bit description of the Host Controller Interface Version Number (HCIVERSION) register.
Table 7: Bit 15 to 0 HCIVERSION register: bit description Symbol Access Value 0100h Description Host Controller Interface Version Number: It contains a BCD encoding of the version number of the interface to which the Host Controller interface conforms. HCIVERSION R [15:0]
8.1.3 HCSPARAMS register (R: 0004h)
The Host Controller Structural Parameters (HCSPARAMS) register is a set of fields that are structural parameters. The bit allocation is given in Table 8.
Table 8: Bit Symbol Reset Access
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HCSPARAMS register: bit allocation 31 0 R 30 0 R 29 0 R 28 reserved 0 R 0 R 0 R 0 R 0 R 27 26 25 24
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21 DPN[3:0] 20 19 18 reserved 0 R 13 N_CC[3:0] 0 R 5 reserved 0 R 0 R 12 0 R 4 PPC 1 R 0 R 0 R 11 0 R 3 0 R 10 N_PCC[3:0] 0 R 2 0 R 0 R 1 0 R 0 R 0 1 R 0 R 9 17 16 P_INDI CATOR 0 R 8
Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
23
22
0 R 15 0 R 7 PRR 0 R Table 9: Bit 31 to 24 23 to 20 19 to 17 16 15 to 12
0 R 14 0 R 6 0 R
N_PORTS[3:0]
HCSPARAMS register: bit description Symbol DPN[3:0] P_INDICATOR N_CC[3:0] Description [1] reserved; write logic 0 Debug Port Number: This field identifies which of the Host Controller ports is the debug port. reserved; write logic 0 Port Indicators: This bit indicates whether the ports support port indicator control. Number of Companion Controller: This field indicates the number of companion controllers associated with this Hi-Speed USB Host Controller. Number of Ports per Companion Controller: This field indicates the number of ports supported per companion Host Controller. Port Routing Rules: This field indicates the method used for mapping ports to the companion controllers. reserved; write logic 0 Port Power Control: This field indicates whether the Host Controller implementation includes port power control. N_Ports: This field specifies the number of physical downstream ports implemented on this Host Controller.
11 to 8 7 6 to 5 4 3 to 0
[1]
N_PCC[3:0] PRR PPC N_PORTS[3:0]
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0.
8.1.4 HCCPARAMS register (R: 0008h)
The Host Controller Capability Parameters (HCCPARAMS) register is a four-byte register, and the bit allocation is given in Table 10.
Table 10: Bit Symbol Reset Access
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HCCPARAMS register: bit allocation 31 0 R 30 0 R 29 0 R 28 reserved 0 R 0 R 0 R 0 R 0 R 27 26 25 24
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21 0 R 13 0 R 5 IST[3:0] 0 R 20 reserved 0 R 12 EECP[7:0] 0 R 4 0 R 19 0 R 11 0 R 3 reserved 0 R 18 0 R 10 0 R 2 ASPC 1 R 17 0 R 9 0 R 1 PFLF 1 R 16 0 R 8 0 R 0 64AC 0 R
Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
23 0 R 15 0 R 7 1 R
22 0 R 14 0 R 6 0 R Table 11: Bit 31 to 16 15 to 8 7 to 4
HCCPARAMS register: bit description Symbol Description [1] reserved; write logic 0
EECP[7:0] EHCI Extended Capabilities Pointer: Default = implementation dependent. This optional field indicates the existence of a capabilities list. IST[3:0] Isochronous Scheduling Threshold: Default = implementation dependent. This field indicates, relative to the current position of the executing Host Controller, where software can reliably update the isochronous schedule. reserved; write logic 0 Asynchronous Schedule Park Capability: Default = implementation dependent. If this bit is set to logic 1, the Host Controller supports the park feature for high-speed queue heads in the Asynchronous Schedule. Programmable Frame List Flag: Default = implementation dependent. If this bit is cleared, the system software must use a frame list length of 1024 elements with this Host Controller. If PFLF is set, the system software can specify and use a smaller frame list and configure the host through the FLS field of the USBCMD register.
3 2
ASPC
1
PFLF
0
[1]
64AC
64-bit Addressing Capability: This field contains the addressing range capability.
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0.
8.2 EHCI operational registers
8.2.1 USBCMD register (R/W: 0020h)
The USB Command (USBCMD) register indicates the command to be executed by the serial Host Controller. Writing to this register causes a command to be executed. Table 12 shows the USBCMD register bit allocation.
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Table 12: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
USBCMD register: bit allocation 31 0 R/W 23 0 R/W 15 0 R/W 7 LHCR 0 R/W 0 R/W 0 R/W 30 0 R/W 22 0 R/W 14 0 R/W 6 29 0 R/W 21 0 R/W 13 0 R/W 5 28 reserved [1] 0 R/W 20 ITC[7:0] 0 R/W 12 reserved [1] 0 R/W 4 reserved [1] 0 R/W 0 R/W 0 R/W 0 R/W 3 0 R/W 2 0 R/W 1 HCRESET 0 R/W 0 R/W 0 RS 0 R/W 1 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 27 26 25 24
The reserved bits should always be written with the reset value.
Table 13: Bit 31 to 24 23 to 16 15 to 8 7
USBCMD register: bit description Symbol ITC[7:0] LHCR Description [1] reserved; write logic 0 Interrupt Threshold Control: This field is used by the system software to select the maximum rate at which the Host Controller will issue interrupts. reserved Light Host Controller Reset (optional): If implemented, it allows the driver software to reset the EHCI controller without affecting the state of the ports or the relationship to the companion Host Controllers. If not implemented, a read of this field will always return logic 0. reserved
6 to 2 1 0
[1]
-
HCRESET Host Controller Reset: This control bit is used by the software to reset the Host Controller. RS Run/Stop: 1 = Run, 0 = Stop. When set, the Host Controller executes the schedule.
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0.
8.2.2 USBSTS register (R/W: 0024h)
The USB Status (USBSTS) register indicates pending interrupts and various states of the Host Controller. The status resulting from a transaction on the serial bus is not indicated in this register. Software clears the register bits by writing ones to them. The bit allocation is given in Table 14.
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Table 14: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
USBSTS register: bit allocation 31 0 R/W 23 0 R/W 15 0 R/W 7 0 R/W 30 0 R/W 22 0 R/W 14 0 R/W 6 reserved [1] 0 R/W 0 R/W 0 R/W 29 0 R/W 21 0 R/W 13 0 R/W 5 28 reserved [1] 0 R/W 20 reserved [1] 0 R/W 12 reserved [1] 1 R/W 4 0 R/W 3 FLR 0 R/W 0 R/W 2 PCD 0 R/W 0 R/W 0 R/W 1 reserved [1] 0 R/W 0 R/W 0 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 27 26 25 24
The reserved bits should always be written with the reset value.
Table 15: Bit 3 2 31 to 4 -
USBSTS register: bit description reserved; write logic 0 Frame List Rollover: The Host Controller sets this bit to logic 1 when the Frame List Index rolls over from its maximum value to zero. Port Change Detect: The Host Controller sets this bit to logic 1 when any port, where the PO bit is cleared, has a change to a one or a FPR bit changes to a one as a result of a J-K transition detected on a suspended port. reserved
Symbol Description [1] FLR PCD
1 to 0
[1]
-
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0.
8.2.3 USBINTR register (R/W: 0028h)
The USB Interrupt Enable (USBINTR) register enables and disables reporting of the corresponding interrupt to the software. When a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt sources that are disabled in this register still appear in USBSTS to allow the software to poll for events. The USBINTR register bit allocation is given in Table 16.
Table 16: Bit Symbol Reset Access 0 R/W 0 R/W 0 R/W 0 R/W USBINTR register: bit allocation 31 30 29 28 reserved [1] 0 R/W 0 R/W 0 R/W 0 R/W 27 26 25 24
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21 0 R/W 13 0 R/W 5 reserved [1] 0 R/W 20 reserved [1] 0 R/W 12 reserved [1] 0 R/W 4 0 R/W 19 0 R/W 11 0 R/W 3 FLRE 0 R/W 18 0 R/W 10 0 R/W 2 PCIE 0 R/W 0 R/W 17 0 R/W 9 0 R/W 1 reserved [1] 0 R/W 16 0 R/W 8 0 R/W 0
Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
23 0 R/W 15 0 R/W 7 0 R/W
22 0 R/W 14 0 R/W 6 0 R/W
The reserved bits should always be written with the reset value.
Table 17: Bit 31 to 4 3
USBINTR register: bit description Symbol FLRE Description [1] reserved Frame List Rollover Enable: When this bit is set and the FLR bit in the USBSTS register is set, the Host Controller issues an interrupt. The interrupt is acknowledged by software clearing bit FLR. Port Change Interrupt Enable: When this bit is set and the PCD bit in the USBSTS register is set, the Host Controller issues an interrupt. The interrupt is acknowledged by software clearing bit PCD. reserved
2
PCIE
1 to 0
[1]
-
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0.
8.2.4 FRINDEX register (R/W: 002Ch)
The Frame Index (FRINDEX) register is used by the Host Controller to index into the periodic frame list. The register updates every 125 s (once each microframe). Bits n to 3 are used to select a particular entry in the Periodic Frame List during periodic schedule execution. The number of bits used for the index depends on the size of the frame list as set by the system software in the FLS (Frame List Size) field of the USBCMD register. This register must be written as a Double Word. A Word-only write (16-bit mode) produces undefined results. This register cannot be written unless the Host Controller is in the halted state as indicated by the HCH (HCHalted) bit. A write to this register while the RS (Run/Stop) bit is set produces undefined results. Writes to this register also affect the SOF value. The bit allocation is given in Table 18.
Table 18: Bit Symbol Reset Access 0 R/W 0 R/W 0 R/W 0 R/W FRINDEX register: bit allocation 31 30 29 28 reserved [1] 0 R/W 0 R/W 0 R/W 0 R/W 27 26 25 24
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21 0 R/W 13 0 R/W 5 0 R/W 20 reserved [1] 0 R/W 12 0 R/W 4 0 R/W 19 0 R/W 11 0 R/W 3 0 R/W 18 0 R/W 10 0 R/W 2 0 R/W 17 0 R/W 9 0 R/W 1 0 R/W 16 0 R/W 8 0 R/W 0 0 R/W
Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
23 0 R/W 15 reserved [1] 0 R/W 7 0 R/W
22 0 R/W 14 0 R/W 6 0 R/W
FRINDEX[13:8]
FRINDEX[7:0]
The reserved bits should always be written with the reset value.
Table 19: Bit 13 to 0 31 to 14 -
FRINDEX register: bit description Symbol Description [1] reserved
FRINDEX[13:0] Frame Index: Bits in this register are used for the frame number in the SOF packet and as the index into the Frame List. The value in this register increments at the end of each time frame (for example, microframe).
[1]
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0.
8.2.5 CTRLDSSEGMENT register (R/W: 0030h)
The Control Data Structure Segment (CTRLDSSEGMENT) register corresponds to the most significant address bits (63 to 32) for all EHCI data structures. If the 64AC (64-bit Addressing Capability) field in HCCPARAMS is cleared, then this register is not used and software cannot write to it (reading from this register returns zero). If the 64AC (64-bit Addressing Capability) field in HCCPARAMS is set, this register is used with link pointers to construct 64-bit addresses to EHCI control data structures. This register is concatenated with the link pointer from either the PERIODICLISTBASE, ASYNCLISTADDR, or any control data structure link field to construct a 64-bit address. This register allows the host software to locate all control data structures within the same 4 gigabytes memory segment.
8.2.6 CONFIGFLAG register (R/W: 0060h)
The bit allocation of the Configure Flag (CONFIGFLAG) register is given in Table 20.
Table 20: Bit Symbol Reset Access 0 R/W 0 R/W 0 R/W 0 R/W CONFIGFLAG register: bit allocation 31 30 29 28 reserved [1] 0 R/W 0 R/W 0 R/W 0 R/W 27 26 25 24
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21 0 R/W 13 0 R/W 5 0 R/W 20 reserved [1] 0 R/W 12 reserved [1] 0 R/W 4 reserved [1] 0 R/W 19 0 R/W 11 0 R/W 3 0 R/W 18 0 R/W 10 0 R/W 2 0 R/W 17 0 R/W 9 0 R/W 1 0 R/W 16 0 R/W 8 0 R/W 0 CF 0 R/W
Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
23 0 R/W 15 0 R/W 7 0 R/W
22 0 R/W 14 0 R/W 6 0 R/W
The reserved bits should always be written with the reset value.
Table 21: Bit 31 to 1 0
CONFIGFLAG register: bit description Symbol Description [1] CF reserved Configure Flag: The host software sets this bit as the last action when it is configuring the Host Controller. This bit controls the default port-routing control logic.
[1]
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0.
8.2.7 PORTSC1 register (R/W: 0064h)
The Port Status and Control (PORTSC) register (bit allocation: Table 22) is in the power well. It is reset by hardware only when the auxiliary power is initially applied or in response to a Host Controller reset. The initial conditions of a port are:
* No peripheral connected * Port disabled.
If the port has power control, software cannot change the state of the port until it sets the port power bits. Software must not attempt to change the state of the port until the power is stable on the port (maximum delay is 20 ms from the transition).
Table 22: Bit Symbol Reset Access Bit Symbol Reset Access 0 R/W 0 R/W 0 R/W 23 0 R/W 22 reserved [1] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 21 0 R/W 20 PORTSC1 register: bit allocation 31 30 29 28 reserved [1] 0 R/W 19 0 R/W 18 PTC[3:0] 0 R/W 0 R/W 0 R/W 17 0 R/W 16 27 26 25 24
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13 PO 1 R/W 5 0 R/W 12 PP 0 R/W 4 reserved [1] 0 R/W 0 R/W 0 R/W 3 11 LS[1:0] 0 R/W 2 PED 0 R/W 10 9 reserved [1] 0 R/W 1 ECSC 0 R/W 8 PR 0 R 0 ECCS 0 R
Bit Symbol Reset Access Bit Symbol Reset Access
[1]
15 PIC[1:0] 0 R 7 SUSP 0 R/W
14 0 R 6 FPR 0 R/W
The reserved bits should always be written with the reset value.
Table 23: Bit 31 to 20 19 to 16
PORTSC1 register: bit description Symbol PTC[3:0] Description [1] reserved Port Test Control: When this field is zero, the port is not operating in a test mode. A non-zero value indicates that it is operating in test mode indicated by the value. Port Indicator Control: Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is logic 0. For a description on how these bits are implemented, refer to Universal Serial Bus Specification Rev. 2.0. [2]
15 to 14
PIC[1:0]
13
PO
Port Owner: This bit unconditionally goes to logic 0 when the configured bit in the CONFIGFLAG register makes a logic 0 to logic 1 transition. This bit unconditionally goes to logic 1 whenever the configured bit is logic 0. Port Power: The function of this bit depends on the value of the PPC (Port Power Control) field in the HCSPARAMS register. Line Status: This field reflect the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. reserved Port Reset: Logic 1 means the port is in the reset state. Logic 0 means the port is not in reset. [2] Suspend: Logic 1 means the port is in the suspend state. Logic 0 means the port is not suspended. [2] Force Port Resume: Logic 1 means resume detected or driven on the port. Logic 0 means no resume (K-state) detected or driven on the port. [2] reserved Port Enabled/Disabled: Logic 1 means enable. Logic 0 means disable. [2] Connect Status Change: Logic 1 means change in ECCS. Logic 0 means no change. [2] Current Connect Status: Logic 1 indicates a device is present on the port. Logic 0 indicates no device is present. [2]
12 11 to 10 9 8 7 6 5 to 3 2 1 0
[1] [2]
PP LS[1:0] PR SUSP FPR PED ECSC ECCS
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0. These fields read logic 0, if the PP (Port Power) bit in register PORTSC1 is logic 0.
8.2.8 ISO PTD Done Map register (R: 0130h)
The bit description of the register is given in Table 24.
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ISO PTD Done Map register: bit description Symbol ISO_PTD_DONE_ MAP[31:0] Access Value R Description 0000 0000h ISO PTD Done Map: Done map for each of the 32 PTDs for the ISO transfer
Table 24: Bit 31 to 0
This register represents a direct map of the done status of the 32 PTDs. The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. Reading the Done Map register will clear all the bits that are set to logic 1, and the next reading will reflect the updated status of new executed PTDs.
8.2.9 ISO PTD Skip Map register (R/W: 0134h)
Table 25 shows the bit description of the register.
Table 25: Bit 31 to 0 ISO PTD Skip Map register: bit description Symbol ISO_PTD_SKIP_ MAP[31:0] Access R/W Value FFFF FFFFh Description ISO PTD Skip Map: Skip map for each of the 32 PTDs for the ISO transfer.
When a bit in the PTD Skip Map is set to logic 1 that PTD will be skipped although its V bit may be set. The information in that PTD is not processed. For example, NextPTDPointer will not affect the order of processing of PTDs. The Skip bit should not be normally set on the position indicated by NextPTDPointer.
8.2.10 ISO PTD Last PTD register (R/W: 0138h)
Table 26 shows the bit description of the ISO PTD Last PTD register.
Table 26: Bit 31 to 0 ISO PTD Last PTD register: bit description Symbol ISO_PTD_LAST_ PTD[31:0] Access R/W Value 0000 0000h Description ISO PTD last PTD: Last PTD of the 32 PTDs is indicated by the 32 bitmap. 1h -- One PTD in ISO 2h -- Two PTDs in ISO 4h -- Three PTDs in ISO.
Once the LastPTD bit corresponding to a PTD is set, this will be the last PTD processed (checking V = 1) in that PTD category. Subsequently, the process will restart with the first PTD (of that group). This is useful to reduce the time in which all the PTDs (the respective memory space) would be checked, especially if only a few PTDs are defined. The LastPTD bit must be normally set to a higher position than any other position indicated by the NextPTDPointer from an active PTD.
8.2.11 INT PTD Done Map register (R: 0140h)
The bit description of the register is given in Table 27.
Table 27: Bit 31 to 0 INT PTD Done Map register: bit description Symbol INT_PTD_DONE_ MAP[31:0] Access R Value Description 0000 0000h INT PTD Done Map: Done map for each of the 32 PTDs for the INT transfer
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This register represents a direct map of the done status of the 32 PTDs. The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. Reading the Done Map register will clear all the bits that are set to logic 1, and the next reading will reflect the updated status of new executed PTDs.
8.2.12 INT PTD Skip Map register (R/W: 0144h)
Table 28 shows the bit description of the INT PTD Skip Map register.
Table 28: Bit 31 to 0 INT PTD Skip Map register: bit description Symbol INT_PTD_SKIP_ MAP[31:0] Access R/W Value FFFF FFFFh Description INT PTD Skip Map: Skip map for each of the 32 PTDs for the INT transfer
When a bit in the PTD Skip Map is set to logic 1 that PTD will be skipped although its V bit may be set. The information in that PTD is not processed. For example, NextPTDPointer will not affect the order of processing of PTDs. The Skip bit should not be normally set on the position indicated by NextPTDPointer.
8.2.13 INT PTD Last PTD register (R/W: 0148h)
The bit description of the register is given in Table 29.
Table 29: Bit 31 to 0 INT PTD Last PTD register: bit description Symbol INT_PTD_LAST _PTD[31:0] Access R/W Value Description 0000 0000h INT PTD Last PTD: Last PTD of the 32 PTDs as indicated by the 32 bitmap. 1h -- One PTD in INT 2h -- Two PTDs in INT 3h -- Three PTDs in INT.
Once the LastPTD bit corresponding to a PTD is set, this will be the last PTD processed (checking V = 1) in that PTD category. Subsequently, the process will restart with the first PTD (of that group). This is useful to reduce the time in which all the PTDs (the respective memory space) would be checked, especially if only a few PTDs are defined. The LastPTD bit must be normally set to a higher position than any other position indicated by the NextPTDPointer from an active PTD.
8.2.14 ATL PTD Done Map register (R: 0150h)
Table 30 shows the bit description of the ATL PTD Done Map register.
Table 30: Bit ATL PTD Done Map register: bit description Access R Value 0000 0000h Description ATL PTD Done Map: Done map for each of the 32 PTDs for the ATL transfer
Symbol
31 to 0 ATL_PTD_DONE _MAP[31:0]
This register represents a direct map of the done status of the 32 PTDs. The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. Reading the Done Map register will clear all the bits that are set to logic 1, and the next reading will reflect the updated status of new executed PTDs.
8.2.15 ATL PTD Skip Map register (R/W: 0154h)
The bit description of the register is given in Table 31.
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ATL PTD Skip Map register: bit description Access Value R/W FFFF FFFFh Description ATL PTD Skip Map: Skip map for each of the 32 PTDs for the ATL transfer
Table 31: Bit
Symbol
31 to 0 ATL_PTD_SKIP _MAP[31:0]
When a bit in the PTD Skip Map is set to logic 1 that PTD will be skipped although its V bit may be set. The information in that PTD is not processed. For example, NextPTDPointer will not affect the order of processing of PTDs. The Skip bit should not be normally set on the position indicated by NextPTDPointer.
8.2.16 ATL PTD Last PTD register (R/W: 0158h)
The bit description of the ATL PTD Last PTD register is given in Table 32.
Table 32: Bit 31 to 0 ATL PTD Last PTD register: bit description Symbol ATL_PTD_ LAST_PTD [31:0] Access R/W Value 0000 0000h Description ATL PTD Last PTD: Last PTD of the 32 PTDs as indicated by the 32 bitmap. 1h -- One PTD in ATL 2h -- Two PTDs in ATL 4h -- Three PTDs in ATL.
Once the LastPTD bit corresponding to a PTD is set, this will be the last PTD processed (checking V = 1) in that PTD category. Subsequently, the process will restart with the first PTD (of that group). This is useful to reduce the time in which all the PTDs (the respective memory space) would be checked, especially if only a few PTDs are defined. The LastPTD bit must be normally set to a higher position than any other position indicated by the NextPTDPointer from an active PTD.
8.3 Configuration registers
8.3.1 HW Mode Control register (R/W: 0300h)
Table 33 shows the bit allocation of the register.
Table 33: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access 0 R/W 15 ANA_DIGI _OC 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 0 R/W 13 0 R/W 12 reserved [1] 0 R/W 0 R/W 0 R/W HW Mode Control register: bit allocation 31 ALL_ATX_ RESET 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 reserved [1] 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 DATA_BUS _WIDTH 1 R/W 30 29 28 27 reserved [1] 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 26 25 24
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5 DREQ_ POL 0 R/W 0 R/W 4 reserved [1] 0 R/W 3 2 INTR_POL 0 R/W 1 INTR_ LEVEL 0 R/W 0 GLOBAL_ INTR_EN 0 R/W
Bit Symbol Reset Access
[1]
7 reserved 0 R/W
6 DACK_ POL 0 R/W
The reserved bits should always be written with the reset value.
Table 34: Bit 31
HW Mode Control register: bit description Symbol ALL_ATX_ RESET Description All ATX Reset: For debugging purposes (not used normally). 1 -- Enable reset, then write back logic 0 0 -- No reset. reserved; write logic 0 Analog Digital Overcurrent: This bit selects analog or digital overcurrent detection on pins OC1_N, OC2_N and OC3_N. 0 -- Digital overcurrent 1 -- Analog overcurrent.
30 to 16 15
ANA_DIGI_OC
14 to 9 8
DATA_BUS_ WIDTH
reserved; write logic 0 Data Bus Width: 0 -- defines a 16-bit data bus width 1 -- sets a 32-bit data bus width. reserved; write logic 0 DACK Polarity: 1 -- indicates that the DACK input is active HIGH 0 -- indicates active LOW.
7 6
DACK_POL
5
DREQ_POL
DREQ Polarity: 1 -- indicates that the DREQ output is active HIGH 0 -- indicates active LOW.
4 to 3 2
INTR_POL
reserved; write logic 0 Interrupt Polarity: 0 -- active LOW 1 -- active HIGH.
1
INTR_LEVEL
Interrupt Level: 0 -- INT level triggered 1 -- INT is edge triggered. A pulse of certain width is generated.
0
GLOBAL_INTR Global Interrupt Enable: This bit must be set to logic 1 to enable the _EN IRQ signal assertion. 0 -- IRQ assertion is disabled. IRQ will never be asserted, regardless of other settings or IRQ events. 1 -- IRQ assertion is enabled. IRQ will be asserted according to the Interrupt Enable register, and events setting and occurrence.
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8.3.2 Chip ID register (R: 0304h)
Read this register to get the ID of the ISP1760. The upper word of the register contains the hardware version number and the lower word contains the chip ID. Table 35 shows the bit description of the register.
Table 35: Bit Chip ID register: bit description Access Value R 0001 1761h Description Chip ID: This register represents the hardware version number (0001h) and the chip ID (1761h). Remark: The chip ID is for internal use to identify the ISP176x product family.
Symbol
31 to 0 CHIPID [31:0]
8.3.3 Scratch register (R/W: 0308h)
This register is for testing and debugging purposes only. The value read back must be the same as the value that was written. The bit description of this register is given in Table 36.
Table 36: Bit 31 to 0 Scratch register: bit description Symbol SCRATCH[31:0] Access R/W Value 0000 0000h Description Scratch: For testing and debugging purposes
8.3.4 SW Reset register (R/W: 030Ch)
Table 37 shows the bit allocation of the register.
Table 37: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
SW Reset register: bit allocation 31 0 R/W 23 0 R/W 15 0 R/W 7 30 0 R/W 22 0 R/W 14 0 R/W 6 29 0 R/W 21 0 R/W 13 0 R/W 5 reserved [1] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 28 reserved [1] 0 R/W 20 reserved [1] 0 R/W 12 reserved [1] 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 RESET_ HC 0 R/W 0 R/W 0 RESET_ ALL 0 R/W 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 27 26 25 24
The reserved bits should always be written with the reset value.
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SW Reset register: bit description Symbol RESET_HC Description reserved; write logic 0 Reset Host Controller: Reset only the Host Controller-specific registers (only registers with address below 300h). 0 -- No reset 1 -- Enable reset.
Table 38: Bit 31 to 2 1
0
RESET_ALL Reset All: Reset all the Host Controller and CPU interface registers. 0 -- No reset 1 -- Enable reset.
8.3.5 DMA Configuration register (R/W: 0330h)
The bit allocation of the DMA Configuration register is given in Table 39.
Table 39: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol 0 R/W 7 0 R/W 6 reserved [1] 0 R/W 5 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 23 0 R/W 22 0 R/W 21 DMA Configuration register: bit allocation 31 30 29 28 0 R/W 20 0 R/W 12 0 R/W 4 27 0 R/W 19 0 R/W 11 0 R/W 3 26 0 R/W 18 0 R/W 10 0 R/W 2 25 0 R/W 17 0 R/W 9 0 R/W 1 ENABLE_ DMA 0 R/W 24 0 R/W 16 0 R/W 8 0 R/W 0 DMA_READ _WRITE_ SEL 0 R/W DMA_COUNTER[23:16]
DMA_COUNTER[15:8]
DMA_COUNTER[7:0]
BURST_LEN[1:0]
Reset Access
[1]
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
The reserved bits should always be written with the reset value.
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DMA Configuration register: bit description Symbol DMA_COUNTER [23:0] Description DMA Counter: The number of bytes to be transferred (read or write). Remark: Different number of bursts will be generated for the same transfer length programmed in 16-bit and 32-bit modes because DMA_COUNTER is in number of bytes.
Table 40: Bit 31 to 8
7 to 4 3 to 2
BURST_LEN[1:0]
reserved DMA Burst Length: 00 -- Single DMA burst 01 -- 4-cycle DMA burst 10 -- 8-cycle DMA burst 11 -- 16-cycle DMA burst.
1
ENABLE_DMA
Enable DMA: 0 -- Terminate DMA 1 -- Enable DMA.
0
DMA_READ_ WRITE_SEL
DMA Read/Write Select: Indicates if the DMA operation is a write or read (to or from the ISP1760). 0 -- DMA write to the ISP1760 internal RAM is set 1 -- DMA read from the ISP1760 internal RAM.
8.3.6 Buffer Status register (R/W: 0334h)
Table 41 shows the bit allocation of the Buffer Status register.
Table 41: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
Buffer Status register: bit allocation 31 0 R/W 23 0 R/W 15 0 R/W 7 30 0 R/W 22 0 R/W 14 0 R/W 6 29 0 R/W 21 0 R/W 13 0 R/W 5 reserved [1] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 28 reserved [1] 0 R/W 20 reserved [1] 0 R/W 12 reserved [1] 0 R/W 4 0 R/W 3 0 R/W 2 ISO_BUF_ FILL 0 R/W 0 R/W 1 INT_BUF_ FILL 0 R/W 0 R/W 0 ATL_BUF_ FILL 0 R/W 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 27 26 25 24
The reserved bits should always be written with the reset value.
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Buffer Status register: bit description Symbol ISO_BUF_ FILL Description reserved ISO Buffer Filled: 1 -- Indicates one of the ISO PTDs is filled, and the ISO PTD area will be processed 0 -- Indicates there is no PTD in this area. Therefore, processing of the ISO PTDs will be completely skipped.
Table 42: Bit 31 to 3 2
1
INT_BUF_ FILL
INT Buffer Filled: 1 -- Indicates one of the INT PTDs is filled, and the INT PTD area will be processed 0 -- Indicates there is no PTD in this area. Therefore, processing of the INT PTDs will be completely skipped.
0
ATL_BUF_ FILL
ATL Buffer Filled: 1 -- Indicates one of the ATL PTDs is filled, and the ATL PTD area will be processed 0 -- Indicates there is no PTD in this area. Therefore, processing of the ATL PTDs will be completely skipped.
8.3.7 ATL Done Timeout register (R/W: 0338h)
The bit description of the ATL Done Timeout register is given in Table 43.
Table 43: Bit 31 to 0 ATL Done Timeout register: bit description Symbol Access Value Description ATL_DONE R/W _TIMEOUT [31:0] 0000 0000h ATL Done Timeout: This register determines the ATL done timeout interrupt. This register defines the timeout in ms after which the ISP1760 asserts the INT line, if enabled. It is applicable to the ATL done PTDs only.
8.3.8 Memory register (R/W: 033Ch)
The Memory register contains the base memory read address and the respective bank. This register needs to be set only before a first memory read cycle. Once written, the address will be latched for the bank and will be incremented for every read of that bank, until a new address for that bank is written to change the address pointer. The bit description of the register is given in Table 44.
Table 44: Bit Symbol Reset Access Bit Symbol Reset Access 0 R/W 0 R/W 0 R/W 0 R/W 23 0 R/W 22 0 R/W 21 reserved [1] 0 R/W 0 R/W 0 R/W 0 R/W 20 Memory register: bit allocation 31 30 29 28 reserved [1] 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 0 R/W 16 0 R/W 27 26 25 24
MEM_BANK_SEL[1:0]
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13 0 R/W 5 0 R/W 12 0 R/W 4 0 R/W 11 0 R/W 3 0 R/W 10 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W
Bit Symbol Reset Access Bit Symbol Reset Access
[1]
15 0 R/W 7 0 R/W
14 0 R/W 6 0 R/W
START_ADDR_MEM_READ[15:8]
START_ADDR_MEM_READ[7:0]
The reserved bits should always be written with the reset value.
Table 45: Bit 31 to 18 17 to 16
Memory register: bit description Symbol MEM_BANK_ SEL[1:0] Description reserved Memory Bank Select: Up to four memory banks can be selected. For details on internal memory read description, see Section 7.3.1. Applicable to PIO mode memory read or write data transfers only.
15 to 0
START_ Start Address for Memory Read Cycles: The start address for a ADDR_MEM_ series of memory read cycles at incremental addresses in a READ[15:0] contiguous space. Applicable to PIO mode memory read data transfers only.
8.3.9 Edge Interrupt Count register (R/W: 0340h)
Table 46 shows the bit allocation of the register.
Table 46: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
Edge Interrupt Count register: bit allocation 31 0 R/W 23 0 R/W 15 0 R/W 7 0 R/W 30 0 R/W 22 0 R/W 14 0 R/W 6 0 R/W 29 0 R/W 21 0 R/W 13 0 R/W 5 0 R/W 28 0 R/W 20 reserved [1] 0 R/W 12 0 R/W 4 0 R/W 0 R/W 11 0 R/W 3 1 R/W 0 R/W 10 0 R/W 2 1 R/W 0 R/W 9 0 R/W 1 1 R/W 0 R/W 8 0 R/W 0 1 R/W 27 0 R/W 19 26 0 R/W 18 25 0 R/W 17 24 0 R/W 16 MIN_WIDTH[7:0]
NO_OF_CLK[15:8]
NO_OF_CLK[7:0]
The reserved bits should always be written with the reset value.
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Edge Interrupt Count register: bit description Symbol MIN_ WIDTH[7:0] Description Minimum Width: Indicates the minimum width between two edge interrupts in SOFs (1 SOF = 125 s). This is not valid for level interrupts. A count of zero means that interrupts occur as and when an event occurs. reserved Number of Clocks: Count in number of clocks that the edge interrupt must be kept asserted on the interface. The default IRQ pulse width is approximately 500 ns.
Table 47: Bit 31 to 24
23 to 16 15 to 0
NO_OF_ CLK[15:0]
8.3.10 DMA Start Address register (W: 0344h)
This register defines the start address select for the DMA read and write operations. See Table 48 for the bit allocation.
Table 48: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
DMA Start Address register: bit allocation 31 0 W 23 0 W 15 0 W 7 0 W 30 0 W 22 0 W 14 0 W 6 0 W 29 0 W 21 0 W 13 0 W 5 0 W 28 reserved [1] 0 W 20 reserved [1] 0 W 12 0 W 4 0 W 0 W 11 0 W 3 0 W 0 W 10 0 W 2 0 W 0 W 9 0 W 1 0 W 0 W 8 0 W 0 0 W 0 W 19 0 W 18 0 W 17 0 W 16 27 26 25 24
START_ADDR_DMA[15:8]
START_ADDR_DMA[7:0]
The reserved bits should always be written with the reset value.
Table 49: Bit 31 to 16 15 to 0
DMA Start Address register: bit description Symbol START_ADDR _DMA[15:0] Description reserved Start Address for DMA: The start address for DMA read or write cycles.
8.3.11 Power Down Control register (R/W: 0354h)
This register is used to turn off power to the internal blocks of the ISP1760 to obtain maximum power savings. Table 50 shows the bit allocation of the register.
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Table 50: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
Power Down Control register: bit allocation 31 0 R/W 23 1 R/W 15 30 0 R/W 22 1 R/W 14 reserved [1] 0 R/W 7 reserved [1] 1 R/W 0 R/W 0 R/W 6 0 R/W 5 BIASEN 1 R/W 29 0 R/W 21 1 R/W 13 28 0 R/W 20 0 R/W 12 PORT3_ PD 1 R/W 4 VREG_ON 0 R/W 27 0 R/W 19 1 R/W 11 PORT2_ PD 1 R/W 3 OC3_PWR 0 R/W 26 0 R/W 18 0 R/W 10 VBATDET_ PWR 0 R/W 2 OC2_PWR 0 R/W 1 R/W 1 OC1_PWR 0 R/W 25 1 R/W 17 0 R/W 9 reserved [1] 1 R/W 0 HC_CLK_ EN 0 R/W 24 1 R/W 16 0 R/W 8 CLK_OFF_COUNTER[15:8]
CLK_OFF_COUNTER[7:0]
The reserved bits should always be written with the reset value.
Table 51: Bit [1] 31 to 16
Power Down Control register: bit description Symbol CLK_OFF _COUNTER [15:0] Description Clock Off Counter: Determines the wake-up status duration after any wake-up event before the ISP1760 goes back into suspend mode. This timeout is applicable only if, during the given interval, the Host Controller is not programmed back to the normal functionality. 03E8h -- The default value. It determines the default wake-up interval of 10 ms. A value of zero implies that the Host Controller never wakes up on any of the events. This may be useful when using the ISP1760 as a peripheral to save power by permanently programming the Host Controller in suspend. FFFFh -- The maximum value. It determines a maximum wake-up time of 500 ms. The setting of this register is based on the 100 kHz 40 % LazyClock frequency. It is a multiple of 10 s period. In 16-bit mode, a write operation to these bits with any value will determine a fixed wake-up time of 50 ms.
15 to 13 12
PORT3_ PD
reserved Port 3 Pull-Down: Controls port 3 pull-down resistors. 0 -- Port 3 pull-down resistors are connected in suspend 1 -- Port 3 pull-down resistors are not connected in suspend. Port 2 Pull-Down: Controls port 2 pull-down resistors. 0 -- Port 2 internal pull-down resistors are connected in suspend 1 -- Port 2 internal pull-down resistors are not connected in suspend.
11
PORT2_ PD
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Power Down Control register: bit description...continued Symbol VBATDET_ PWR Description VBAT Detector Powered: Controls the power to the VBAT detector. 0 -- VBAT detector is powered or enabled in suspend 1 -- VBAT detector is not powered or disabled in suspend. reserved; write logic 0 BIAS Circuits Powered: Controls the power to internal BIAS circuits. 0 -- Internal BIAS circuits are not powered in suspend 1 -- Internal BIAS circuits are powered in suspend.
Table 51: Bit [1] 10
9 to 6 5
BIASEN
4
VREG_ON
VREG Powered: Enables or disables the internal 3.3 V and 1.8 V regulators when the ISP1760 is in suspend. 0 -- Internal regulators are powered in suspend 1 -- Internal regulators are not powered in suspend.
3
OC3_PWR
OC3_N Powered: Controls the powering of the overcurrent detection circuitry for port 3. 0 -- Overcurrent detection is powered on or enabled during suspend. 1 -- Overcurrent detection is powered off or disabled during suspend. This may be useful when connecting a faulty device while the system is in standby.
2
OC2_PWR
OC2_N Powered: Controls the powering of the overcurrent detection circuitry for port 2. 0 -- Overcurrent detection powered-on or enabled during suspend. 1 -- Overcurrent detection powered-off or disabled during suspend. This may be useful when connecting a faulty device while the system is in standby.
1
OC1_PWR
OC1_N Powered: Controls the powering of the overcurrent detection circuitry for port 1. 0 -- Overcurrent detection powered-on or enabled during suspend. 1 -- Overcurrent detection powered-off or disabled during suspend. This may be useful when connecting a faulty device while the system is in standby.
0
HC_CLK_ EN
Host Controller Clock Enabled: Controls internal clocks during suspend. 0 -- Clocks are disabled during suspend. This is the default value. Only the LazyClock of 100 kHz 40 % will be left running in suspend if this bit is logic 0. If clocks are stopped during suspend, CLKREADY IRQ will be generated when all clocks are running stable. 1 -- All clocks are enabled even in suspend.
[1]
For a 32-bit operation, the default wake-up counter value is 10 s. For a 16-bit operation, the wake-up counter value is 50 ms. In the 16-bit operation, read and write back the same value on initialization.
8.3.12 Port 1 Control register (R/W: 0374h)
The values read from the lower 16 bits and the upper 16 bits of this register are always the same. Table 52 shows the bit allocation of the register.
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Table 52: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
Port 1 Control register: bit allocation 31 0 R/W 23 PORT1_ INIT2 1 R/W 15 0 R/W 7 PORT1_ INIT1 0 R/W 0 R/W 0 R/W 14 0 R/W 6 reserved [1] 0 R/W 0 R/W 13 0 R/W 5 0 R/W 12 reserved [1] 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 reserved [1] 1 R/W 1 R/W 0 R/W 0 R/W 0 30 0 R/W 22 29 0 R/W 21 28 reserved [1] 0 R/W 20 0 R/W 19 reserved [1] 0 R/W 11 1 R/W 10 1 R/W 9 0 R/W 8 0 R/W 18 0 R/W 17 0 R/W 16 27 26 25 24
PORT1_POWER[1:0] 1 R/W 0 R/W
The reserved bits should always be written with the reset value.
Table 53: Bit [1] 23 22 to 8 7 31 to 24 -
Port 1 Control register: bit description Symbol PORT1_ INIT2 PORT1_ INIT1 Description reserved; write logic 0 Port 1 Initialization 2: Write logic 1 at the ISP1760 initialization. It will clear both this bit and bit 7. Affects only port 1. reserved; write logic 0 Port 1 Initialization 1: Must be reset to logic 0 at power-up initialization for correct operation of port 1. Correct Host Controller functionality is not ensured if set to logic 1 (affects only port 1). To clear this bit, logic 1 must be written to bit 23 during the ISP1760 initialization. This is not required for the normal functionality of port 2 and port 3. reserved
6 to 5 4 to 3 2 to 0
[1]
-
PORT1_ Port 1 Power: Set these bits to 11b. These bits must be set to enable POWER[1:0] port 1 power. reserved; write logic 0
For correct port 1 initialization, write 0080 0018h to this register after power on.
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8.4 Interrupt registers
8.4.1 Interrupt register (R/W: 0310h)
The bits of this register indicate the interrupt source, defining the events that determined the INT generation. Clearing the bits that were set because of the events listed is done by writing back logic 1 to the respective position. All bits must be reset before enabling new interrupt events. These bits will be set, regardless of the setting of bit GLOBAL_INTR_EN in the HW Mode Control register. Table 54 shows the bit allocation of the Interrupt register.
Table 54: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
Interrupt register: bit allocation 31 0 R/W 23 0 R/W 15 0 R/W 7 INT_IRQ 0 R/W 30 0 R/W 22 0 R/W 14 0 R/W 6 CLK READY 0 R/W 29 0 R/W 21 0 R/W 13 reserved [1] 0 R/W 5 HC_SUSP 0 R/W 0 R/W 4 reserved [1] 0 R/W 0 R/W 3 DMA EOTINT 0 R/W 0 R/W 0 R/W 2 reserved [1] 0 R/W 28 reserved [1] 0 R/W 20 reserved [1] 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 ISO_IRQ 0 R/W 1 0 R/W 8 ATL_IRQ 0 R/W 0 SOFITLINT 0 R/W 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 27 26 25 24
The reserved bits should always be written with the reset value.
Table 55: Bit 31 to 10 9
Interrupt register: bit description Symbol ISO_IRQ Description reserved; write logic 0 ISO IRQ: Indicates that an IRQ was asserted because an ISO PTD was completed, or the PTDs corresponding to the bits set in the ISO IRQ Mask AND or ISO IRQ Mask OR register bits combination were completed. 0 -- No IRQ assertion determined by the completion of ISO PTDs 1 -- IRQ asserted because of completing ISO PTDs. For details, see Section 7.4.
8
ATL_IRQ
ATL IRQ: Indicates that an IRQ was asserted because an ATL PTD was completed, or the PTDs corresponding to the bits set in the ATL IRQ Mask AND or ATL IRQ Mask OR register bits combination were completed. 0 -- No IRQ assertion determined by the completion of ATL PTDs 1 -- IRQ asserted because of completing ATL PTD. For details, see Section 7.4.
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Interrupt register: bit description...continued Symbol INT_IRQ Description INT IRQ: Indicates that an IRQ was asserted because an INT PTD was completed, or the PTDs corresponding to the bits set in the INT IRQ Mask AND or INT IRQ Mask OR register bits combination were completed. 0 -- No IRQ assertion determined by the completion of INT PTDs 1 -- IRQ asserted because of completing INT PTD. For details, see Section 7.4.
Table 55: Bit 7
6
CLKREADY Clock Ready: Indicates that an IRQ was asserted as the internal clock signals are running stable. Useful after a power-on or wake-up cycle. 0 -- No CLKREADY event has occurred 1 -- INT generated because of a CLKREADY event.
5
HC_SUSP
Host Controller Suspend: Indicates that the Host Controller has entered suspend mode. 0 -- No INT generated because of the Host Controller entering suspend mode 1 -- INT generated because of the Host Controller entering suspend mode. If the ISR accesses the ISP1760, it will wake up for the time specified in bits 31 to 16 of the Power Down Control register.
4 3
DMAEOT INT
reserved; write logic 0 DMA EOT Interrupt: Indicates DMA transfer completion. 0 -- DMA transfer is not complete 1 -- IRQ asserted because the DMA transfer is complete. reserved; write logic 0 0 -- No SOF event has occurred 1 -- An SOF event has occurred.
2 to 1 0
-
SOFITLINT SOT ITL Interrupt:
8.4.2 Interrupt Enable register (R/W: 0314h)
This register allows enabling or disabling of the IRQ generation because of various events as described in Table 56.
Table 56: Bit Symbol Reset Access Bit Symbol Reset Access 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 reserved [1] 0 R/W 0 R/W 0 R/W 0 R/W Interrupt Enable register: bit allocation 31 30 29 28 reserved [1] 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 27 26 25 24
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13 reserved [1] 12 11 10 9 ISO_IRQ_ E 0 R/W 4 reserved [1] 0 R/W 0 R/W 3 DMAEOT INT _E 0 R/W 0 R/W 0 R/W 2 reserved [1] 0 R/W 0 R/W 1 8 ATL_IRQ _E 0 R/W 0 SOFITLINT _E 0 R/W
Bit Symbol Reset Access Bit Symbol Reset Access
[1]
15
14
0 R/W 7 INT_IRQ_E 0 R/W
0 R/W 6 CLK READY _E 0 R/W
0 R/W 5 HCSUSP_ E 0 R/W
The reserved bits should always be written with the reset value.
Table 57: Bit 31 to 10 9
Interrupt Enable register: bit description Symbol ISO_IRQ_E Description reserved; write logic 0 ISO IRQ Enable: Controls the IRQ assertion because of completing one or more ISO PTDs matching the ISO IRQ Mask AND or ISO IRQ Mask OR register bits combination. 0 -- No IRQ will be asserted because of completing ISO PTDs 1 -- IRQ will be asserted. For details, see Section 7.4.
8
ATL_IRQ_E
ATL IRQ Enable: Controls the IRQ assertion because of completing one or more ATL PTDs matching the ATL IRQ Mask AND or ATL IRQ Mask OR register bits combination. 0 -- No IRQ will be asserted because of completing ATL PTDs 1 -- IRQ will be asserted. For details, see Section 7.4.
7
INT_IRQ_E
INT IRQ Enable: Controls the IRQ assertion because of completing one or more INT PTDs matching the INT IRQ Mask AND or INT IRQ Mask OR register bits combination. 0 -- No IRQ will be asserted because of completing INT PTDs 1 -- IRQ will be asserted. For details, see Section 7.4.
6
CLKREADY _E
Clock Ready Enable: Enables the IRQ assertion when internal clock signals are running stable. Useful after power-on or wake-up. 0 -- No IRQ will be generated after a CLKREADY_E event has occurred 1 -- IRQ will be generated after a CLKREADY_E event.
5
HCSUSP_E Host Controller Suspend Enable: Enables the IRQ generation when the Host Controller enters suspend mode. 0 -- No IRQ will be generated because of the Host Controller entering suspend mode 1 -- IRQ will be generated at the Host Controller entering suspend mode.
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Interrupt Enable register: bit description...continued Symbol DMAEOT INT_E Description reserved; write logic 0 DMA EOT Interrupt Enable: Controls assertion of IRQ on the DMA transfer completion. 0 -- No IRQ will be generated after the DMA transfer is completed 1 -- IRQ will be asserted because of the DMA transfer completion.
Table 57: Bit 4 3
2 to 1 0
SOFITLINT _E
reserved; must be written with logic 0 SOT ITL Interrupt Enable: Controls the IRQ generation at every SOF occurrence. 0 -- No IRQ will be generated on an SOF occurrence 1 -- IRQ will be asserted at every SOF.
8.4.3 ISO IRQ Mask OR register (R/W: 0318h)
Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a hardware IRQ mask for each PTD done map. See Table 58 for bit description. For details, see Section 7.4.
Table 58: Bit ISO IRQ Mask OR register: bit description Access Value R/W 0000 0000h Description ISO IRQ Mask OR: Represents a direct map for ISO PTDs 31 to 0. 0 -- No OR condition defined between ISO PTDs 1 -- The bits corresponding to certain PTDs are set to logic 1 to define a certain OR condition.
Symbol
31 to 0 ISO_IRQ_ MASK_OR [31:0]
8.4.4 INT IRQ Mask OR register (R/W: 031Ch)
Each bit of this register (see Table 59) corresponds to one of the 32 INT PTDs defined, and is a hardware IRQ mask for each PTD done map. For details, see Section 7.4.
Table 59: Bit INT IRQ Mask OR register: bit description Access Value 0000 0000h Description INT IRQ Mask OR: Represents a direct map for INT PTDs 31 to 0. 0 -- No OR condition defined between INT PTDs 31 to 0 1 -- The bits corresponding to certain PTDs are set to logic 1 to define a certain OR condition.
Symbol
31 to 0 INT_IRQ_ R/W MASK_OR [31:0]
8.4.5 ATL IRQ Mask OR register (R/W: 0320h)
Each bit of this register corresponds to one of the 32 ATL PTDs defined, and is a hardware IRQ mask for each PTD done map. See Table 60 for bit description. For details, see Section 7.4.
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ATL IRQ Mask OR register: bit description Access Value Description 0000 0000h ATL IRQ Mask OR: Represents a direct map for ATL PTDs 31 to 0. 0 -- No OR condition defined between the ATL PTDs 1 -- The bits corresponding to certain PTDs are set to logic 1 to define a certain OR condition.
Table 60: Bit
Symbol
31 to 0 ATL_IRQ_ R/W MASK_OR [31:0]
8.4.6 ISO IRQ Mask AND register (R/W: 0324h)
Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a hardware IRQ mask for each PTD done map. For details, see Section 7.4. Table 61 provides the bit description of the register.
Table 61: Bit ISO IRQ Mask AND register: bit description Access Value 0000 0000h Description ISO IRQ Mask AND: Represents a direct map for ISO PTDs 31 to 0. 0 -- No AND condition defined between ISO PTDs 1 -- The bits corresponding to certain PTDs are set to logic 1 to define a certain AND condition between the 32 INT PTDs.
Symbol
31 to 0 ISO_IRQ_ R/W MASK_ AND[31:0]
8.4.7 INT IRQ Mask AND register (R/W: 0328h)
Each bit of this register (see Table 62) corresponds to one of the 32 INT PTDs defined, and is a hardware IRQ mask for each PTD done map. For details, see Section 7.4.
Table 62: Bit INT IRQ Mask AND register: bit description Access Value Description 0000 0000h INT IRQ Mask AND: Represents a direct map for INT PTDs 31 to 0. 0 -- No OR condition defined between INT PTDs 1 -- The bits corresponding to certain PTDs are set to logic 1 to define a certain AND condition between the 32 INT PTDs.
Symbol
31 to 0 INT_IRQ_ R/W MASK_ AND[31:0]
8.4.8 ATL IRQ Mask AND register (R/W: 032Ch)
Each bit of this register corresponds to one of the 32 ATL PTDs defined, and is a hardware IRQ mask for each PTD done map. For details, see Section 7.4. Table 63 shows the bit description of the register.
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ATL IRQ Mask AND register: bit description Access Value Description 0000 0000h ATL IRQ Mask AND: Represents a direct map for ATL PTDs 31 to 0. 0 -- No OR condition defined between ATL PTDs 1 -- The bits corresponding to certain PTDs are set to logic 1 to define a certain AND condition between the 32 ATL PTDs.
Table 63: Bit
Symbol
31 to 0 ATL_IRQ_ R/W MASK_ AND[31:0]
9. Philips Transfer Descriptor
The standard EHCI data structures as described in Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 are optimized for the bus master operation that is managed by the hardware state machine. The PTD structures of the ISP1760 are translations of the EHCI data structures that are optimized for the ISP1760, while keeping the architecture of the EHCI data structures the same. This is because the ISP1760 is a slave Host Controller and has no bus master capability. EHCI manages schedules in two lists: periodic and asynchronous. The data structures are designed to provide the maximum flexibility required by USB, minimize memory traffic, and hardware and software complexity. The ISP1760 controller executes transactions for devices by using a simple shared-memory schedule. This schedule consists of data structures organized into three lists. qISO -- Isochronous transfer qINTL -- Interrupt transfer qATL -- Asynchronous transfer; for the control and bulk transfers. The system software maintains two lists for the Host Controller: periodic and asynchronous. The root of the periodic schedule--the PERIODICLISTBASE register--is the physical memory base address of the periodic frame list. The periodic frame list is an array memory pointer. The objects referenced from the frame list must be valid schedule data structures. The asynchronous list base is also a common list of queue heads (endpoints) that are served in a schedule. These endpoint data structures are further linked to the EHCI transfer descriptor that is the valid schedule (queue PTD). The Periodic Schedule Enable (ISO_BUF_FULL and INT_BUF_FULL) or Asynchronous Schedule Enable (ATL_BUF_FULL) bits can enable traversal to these lists. Enabling a list indicates the presence of valid schedule in the list. The system software starts at these points, schedules the first transfer inside the shared memory of the ISP1760, and sets up the ATL, INTL or ITL bit corresponding to the type of transfer scheduled in the shared memory. The ISP1760 has a maximum of 32 ISO, 32 INTL and 32 ATL PTDs. These PTDs are used as channels to transfer data from the shared memory to the USB bus. These channels are allocated and deallocated on receiving the transfer from the core USB driver.
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Multiple transfers are scheduled to the shared memory for various endpoints by traversing the next link pointer provided by the EHCI data structure, until it reaches the terminate bit in a microframe. If a schedule is enabled, the Host Controller starts executing from the ISO schedule, before it goes to the INTL schedule, and then to the ATL schedule. The EHCI periodic and asynchronous lists are traversed by the software according to the EHCI traversal rule, and executed only from the asynchronous schedule after it encounters the end of the periodic schedule. The Host Controller traverses the ISO, INTL and ATL schedules. It fetches the element and begins traversing the graph of linked schedule data structures. The last bit identifies the end of the schedule for each type of transfer, indicating the rest of the channels are empty. Once a transition is completed, the Host Controller executes from the next transfer descriptor in the schedule until the end of the microframe. The completion of a transfer is indicated to the software by the interrupt that can be grouped over the various PTDs by using the AND or OR registers that are available for each schedule type (ISO, INTL and ATL). These registers are simple logic registers to decide the group and individual PTDs that can interrupt the CPU for a schedule, when the logical conditions of the done bit is true in the shared memory that completes the interrupt. Interrupts are of four types and the latency can be programmed in multiples of SOF (125 s).
* * * *
ISO interrupt INTL interrupt ATL Interrupt SOF--start of frame interrupt for the data transfer.
A static PTD that schedules inside the ISP1760 shared memory allows using the NextPTD mechanism that will enable the Host Controller driver to schedule the multiple PTDs that are of single endpoint and reduce the interrupt to the CPU. The NextPTD traversal rules defined by the ISP1760 hardware are: 1. Start the ATL header traversal. 2. If the current PTD is active and not done, perform the transaction. 3. Follow the next link pointer. 4. If PTD is not active and done, jump to the next PTD. 5. If the next link pointer is NULL, it means the end of the traversal.
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Embedded Hi-Speed USB host controller
START PTD SCHEDULE
follow the next link pointer
follow the next link pointer
no
PTD DONE?
yes
INCREMENT THE PTD horizontal link pointer EXECUTE THE PTD null pointer(1) END THE SCHEDULE END THE SCHEDULE
004aaa585
vertical link pointer EXECUTE THE PTD
(1) The NULL pointer terminates goes to the next link.
Fig 10. NextPTD traversal rule.
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9.1 High-speed bulk IN and OUT, Queue Head Asynchronous (QHA) (patent-pending)
Table 64: Bit DW7 DW5 DW3 DW1 A H B X
[1]
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High-speed bulk IN and OUT, QHA: bit allocation 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 reserved reserved P D T Cerr [1:0] reserved NakCnt[3:0] reserved S NrBytesTransferred[14:0] (32 kbytes for high-speed) EP Type [1:0] 13 12 Token [1:0] 11 10 9 DeviceAddress[6:0] EndPt[3:0] 31 to 34 3 2 1 0
63
Bit DW6 DW4 DW2 DW0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
8
7
6
5 J
4
reserved reserved reserved
[2]
NextPTDPointer[4:0] reserved
[1]
RL[3:0]
[1]
DataStartAddress[15:0] NrBytesToTransfer[14:0] (32 kbytes for high-speed)
Mult [1:0]
MaxPacketLength[10:0]
V
[1] [2]
Reserved. EndPt[0].
Embedded Hi-Speed USB host controller
ISP1760
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
Table 65: Bit DW7 63 to 32 DW6 31 to 0 DW5 63 to 32 DW4 31 to 6 5
High-speed bulk IN and OUT, QHA: bit description Symbol reserved reserved reserved reserved J Access SW -- writes Description 0; not applicable for QHA. Jump: 0 -- To increment the PTD pointer 1 -- To enable the next PTD branching.
4 to 0 DW3 63 62 61
NextPTDPointer [4:0] A H B
SW -- writes
Next PTD Counter: Next PTD branching assigned by the PTD pointer.
SW -- sets HW -- resets HW -- writes HW -- writes
Active: Write the same value as that in V. Halt: This bit correspond to the Halt bit of the Status field of QH. Babble: This bit correspond to the Babble Detected bit in the Status field of the iTD, SiTD or QH. 1 -- When babbling is detected, A and V are set to 0. Error: This bit corresponds to the Transaction Error bit in the Status field of iTD, SiTD or QH (Exec_Trans, the signal name is xacterr). 0 -- No PID error. 1 -- If there are PID errors, this bit is set active. The A and V bits are also set to inactive. This transaction is retried three times.
60
X
HW -- writes
59 58
reserved P
HW -- writes
Ping: For high-speed transactions, this bit corresponds to the Ping state bit in the Status field of a QH. 0 -- Ping is not set. 1 -- Ping is set. Software sets this bit to 0.
57
DT
HW -- updates SW -- writes
Data Toggle: This bit is filled by software to start a PTD. If NrBytesToTransfer[14:0] is not complete, software needs to read this value and then write back the same value to continue. Error Counter. This field corresponds to the Cerr[1:0] field in QH. The default value of this field is zero for isochronous transactions. 00 -- The transaction will not retry. 11 -- The transaction will retry three times. Hardware will decrement these values. When the transaction has tried three times, X error will be updated.
56 to 55
Cerr[1:0]
HW -- writes SW -- writes
54 to 51
NakCnt[3:0]
HW -- writes SW -- writes
NAK Counter. This field corresponds to the NAKCnt field in QH. Software writes for the initial PTD launch. The V bit is reset if NakCnt decrements to zero and RL is a non-zero value. It reloads from RL if transaction is ACKed. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
50 to 47
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reserved
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ISP1760
Embedded Hi-Speed USB host controller
Table 65: Bit 46 to 32
High-speed bulk IN and OUT, QHA: bit description...continued Symbol Access Description Number of Bytes Transferred: This field indicates the number of bytes sent or received for this transaction. If Mult[1:0] is greater than one, it is possible to store intermediate results in this field. NrBytesTransferred HW -- writes [14:0] SW -- writes 0000 reserved RL[3:0] reserved DataStartAddress [15:0] SW -- writes SW -- writes
DW2 31 to 29 28 to 25 24 23 to 8 Set to 0 for QHA. Reload: If RL is set to 0h, hardware ignores the NakCnt value. RL and NakCnt are set to the same value before a transaction. Always 0 for QHA. Data Start Address: This is the start address for the data that will be sent or received on or from the USB bus. This is the internal memory address and not the direct CPU address. RAM address = (CPU address - 400h)/8 7 to 0 DW1 63 to 47 46 reserved S SW -- writes Always 0 for QHA. This bit indicates whether a split transaction has to be executed: 0 -- High-speed transaction 1 -- Split transaction. 45 to 44 EPType[1:0] SW -- writes Transaction type: 00 -- Control 10 -- Bulk. 43 to 42 Token[1:0] SW -- writes Token: Identifies the token Packet Identifier (PID) for this transaction: 00 -- OUT 01 -- IN 10 -- SETUP 11 -- PING (written by hardware only). 41 to 35 34 to 32 DW0 31 30 to 29 EndPt[0] Mult[1:0] SW -- writes SW -- writes Endpoint: This is the USB address of the endpoint within the function. Multiplier: This field is a multiplier used by the Host Controller as the number of successive packets the Host Controller may submit to the endpoint in the current execution. For QHA, this is a copy of the Async Schedule Park mode count, if the Async Schedule Park mode is enabled. These EHCI registers need to be set to reflect multiple cycles. Applicable for high-speed only. Set this field to 01b. You can also set it to 11b and 10b depending on your application. 00b is undefined. DeviceAddress[6:0] SW -- writes EndPt[3:1] SW -- writes Device Address: This is the USB address of the function containing the endpoint that is referred to by this buffer. Endpoint: This is the USB address of the endpoint within the function. reserved -
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Embedded Hi-Speed USB host controller
Table 65: Bit 28 to 18
High-speed bulk IN and OUT, QHA: bit description...continued Symbol MaxPacketLength [10:0] Access SW -- writes Description Maximum Packet Length: This field indicates the maximum number of bytes that can be sent to or received from an endpoint in a single data packet. The maximum packet size for a bulk transfer is 512 bytes. The maximum packet size for the isochronous transfer is also variable at any whole number. Number of Bytes to Transfer: This field indicates the number of bytes that can be transferred by this data structure. It is used to indicate the depth of the DATA field (32 kbytes). Valid: 0 -- This bit is deactivated when the entire PTD is executed--across SOF and SOF--or when a fatal error is encountered. 1 -- Software updates to one when there is payload to be sent or received even across ms boundary. The current PTD is active.
17 to 3
NrBytesToTransfer [14:0] reserved V
SW -- writes
2 to 1 0
SW -- sets HW -- resets
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9.2 High-speed isochronous IN and OUT, isochronous Transfer Descriptor (iTD) (patent-pending)
Table 66: Bit DW7 DW5 DW3 DW1 A H B 63 High-speed isochronous IN and OUT, iTD: bit allocation 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 ISOIN_7[11:0] ISOIN_2[7:0] reserved reserved S ISOIN_1[11:0] EP Type [1:0] 13 12 Token [1:0] 11 10 9 ISOIN_6[11:0] ISOIN_5[7:0] ISOIN_0[11:0] NrBytesTransferred[14:0] (32 kbytes for high-speed) DeviceAddress[6:0] EndPt[3:0] 34 to 31 3 2 1 0
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Bit DW6 DW4 DW2 DW0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
8
7
6
5
4
ISOIN_5[3:0] Status7[2:0]
[2]
ISOIN_4[11:0] Status5[2:0] Status4[2:0] Status3[2:0] Status2[2:0] DataStartAddress[15:0] MaxPacketLength[10:0]
ISOIN_3[11:0] Status1[2:0] Status0[2:0]
ISOIN_2[3:0] SA[7:0] Frame[7:0]
[1]
Status6[2:0] reserved
Mult [1:0]
NrBytesToTransfer[14:0] (32 kbytes for high-speed)
V
[1] [2]
Reserved. EndPt[0].
Embedded Hi-Speed USB host controller
ISP1760
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
Table 67: Bit DW7 63 to 52 51 to 40 39 to 32 DW6 31 to 28 27 to 16 15 to 4 3 to 0 DW5 63 to 56 55 to 44 43 to 32 DW4 31 to 29 28 to 26 25 to 23 22 to 20 19 to 17 16 to 14 13 to 11 10 to 8
High-speed isochronous IN and OUT, iTD: bit description Symbol ISOIN_7[11:0] ISOIN_6[11:0] ISOIN_5[7:0] Access HW -- writes HW -- writes HW -- writes Description Bytes received during SOF7, if SA[7] is set to 1 and frame number is correct. Bytes received during SOF6, if SA[6] is set to 1 and frame number is correct. Bytes received during SOF5 (bits 11 to 4), if SA[5] is set to 1 and frame number is correct. Bytes received during SOF5 (bits 3 to 0), if SA[5] is set to 1 and frame number is correct. Bytes received during SOF4, if SA[4] is set to 1 and frame number is correct. Bytes received during SOF3, if SA[3] is set to 1 and frame number is correct. Bytes received during SOF2 (bits 11 to 8), if SA[2] is set to 1 and frame number is correct. Bytes received during SOF2 (bits 7 to 0), if SA[2] is set to 1 and frame number is correct. Bytes received during SOF1, if SA[1] is set to 1 and frame number is correct. Bytes received during SOF0, if SA[0] is set to 1 and frame number is correct. ISO IN or OUT status at SOF7 ISO IN or OUT status at SOF6 ISO IN or OUT status at SOF5 ISO IN or OUT status at SOF4 ISO IN or OUT status at SOF3 ISO IN or OUT status at SOF2 ISO IN or OUT status at SOF1 Status of the payload on the USB bus for this SOF after ISO has been delivered. Bit 0 -- Transaction Error (IN and OUT) Bit 1 -- Babble (IN token only) Bit 2 -- underrun (OUT token only).
ISOIN_5[3:0] ISOIN_4[11:0] ISOIN_3[11:0] ISOIN_2[3:0]
HW -- writes HW -- writes HW -- writes HW -- writes
ISOIN_2[7:0] ISOIN_1[11:0] ISOIN_0[11:0]
HW -- writes HW -- writes HW -- writes
Status7[2:0] Status6[2:0] Status5[2:0] Status4[2:0] Status3[2:0] Status2[2:0] Status1[2:0] Status0[2:0]
HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes
7 to 0
SA[7:0]
SW -- writes (0 => 1) HW -- writes (1 => 0) After processing
SOF Active: When the frame number of bits DW1[7:3] match the frame number of USB bus, these bits are checked for 1 before they are sent for SOF. For example: If SA[7:0] = 1, 1, 1, 1, 1, 1, 1, 1: send ISO every SOF of the entire ms. If SA[7:0] = 0, 1, 0, 1, 0, 1, 0, 1: send ISO only on SOF0, SOF2, SOF4 and SOF6.
DW3 63 62 A H SW -- sets HW -- writes Active: This bit is the same as the Valid bit. Halt: Only one bit for the entire ms. When this bit is set, the Valid bit is reset. The device decides to stall an endpoint.
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Embedded Hi-Speed USB host controller
Table 67: Bit 61 60 to 47 46 to 32
High-speed isochronous IN and OUT, iTD: bit description...continued Symbol B reserved Access HW -- writes Description Babble: Not applicable here. Set to 0 for isochronous. Number of Bytes Transferred: This field indicates the number of bytes sent or received for this transaction. If Mult[1:0] is greater than one, it is possible to store intermediate results in this field. NrBytesTransferred[14:0] is 32 kbytes per PTD. Set to 0 for isochronous. Data Start Address: This is the start address for the data that will be sent or received on or from the USB bus. This is the internal memory address and not the direct CPU address. RAM address = (CPU address - 400h)/8 Bits 2 to 0 -- Don't care Bits 7 to 3 -- Frame number that this PTD will be sent for ISO OUT or IN.
NrBytesTransferred HW -- writes [14:0]
DW2 31 to 24 23 to 8 reserved DataStartAddress [15:0] SW -- writes
7 to 0
Frame[7:0]
SW -- writes
DW1 63 to 47 46 reserved S SW -- writes This bit indicates whether a split transaction has to be executed. 0 -- High-speed transaction 1 -- Split transaction. 45 to 44 43 to 42 EPType[1:0] Token[1:0] SW -- writes SW -- writes Endpoint type: 01 -- Isochronous. Token: This field indicates the token PID for this transaction: 00 -- OUT 01 -- IN. 41 to 35 34 to 32 DW0 31 30 to 29 EndPt[0] Mult[1:0] SW -- writes SW -- writes Endpoint: This is the USB address of the endpoint within the function. This field is a multiplier counter used by the Host Controller as the number of successive packets the Host Controller may submit to the endpoint in the current execution. For isochronous OUT and IN: If Mult[1:0] is 01 -- Data Toggle is Data0 If Mult[1:0] is 10 -- Data Toggle is Data1 If Mult[1:0] is 11 -- Data Toggle is Data2, and so on. For details, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 Appendix D. 28 to 18 MaxPacketLength [10:0] SW -- writes Maximum Packet Length: This field indicates the maximum number of bytes that can be sent to or received from the endpoint in a single data packet. The maximum packet size for an isochronous transfer is 1024 bytes. The maximum packet size for the isochronous transfer is also variable at any whole number. DeviceAddress[6:0] SW -- writes EndPt[3:1] SW -- writes Device Address: This is the USB address of the function containing the endpoint that is referred to by this buffer. Endpoint: This is the USB address of the endpoint within the function.
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Embedded Hi-Speed USB host controller
Table 67: Bit 17 to 3
High-speed isochronous IN and OUT, iTD: bit description...continued Symbol NrBytesToTransfer [14:0] reserved V Access SW -- writes Description Number of Bytes Transferred: This field indicates the number of bytes that can be transferred by this data structure. It is used to indicate the depth of the DATA field (32 kbytes). 0 -- This bit is deactivated when the entire PTD is executed--across SOF and SOF--or when a fatal error is encountered. 1 -- Software updates to one when there is payload to be sent or received even across ms boundary. The current PTD is active.
2 to 1 0
HW -- resets SW -- sets
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9.3 High-speed interrupt IN and OUT, Queue Head Periodic (QHP) (patent-pending)
Table 68: Bit DW7 DW5 DW3 DW1 A H 63 High-speed interrupt IN and OUT, QHP: bit allocation 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 INT_IN_7[11:0] INT_IN_2[7:0] reserved D T Cerr [1:0] reserved INT_IN_1[11:0] reserved S INT_IN_6[11:0] INT_IN_5[7:0] INT_IN_0[11:0] NrBytesTransferred[14:0] (32 kbytes for high-speed) EP Type [1:0] 13 12 Token [1:0] 11 10 9 DeviceAddress[6:0] EndPt[3:0] 31 to 34 3 2 1 0
Product data sheet Rev. 01 -- 8 November 2004 66 of 105
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Bit DW6 DW4 DW2 DW0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
8
7
6
5
4
INT_IN_5[3:0] Status7[2:0]
[2]
INT_IN_4[11:0] Status5[2:0] Status4[2:0] Status3[2:0] Status2[2:0] DataStartAddress[15:0] MaxPacketLength[10:0]
INT_IN_3[11:0] Status1[2:0] Status0[2:0]
INT_IN_2[3:0] SA[7:0] Frame[7:0]
[1]
Status6[2:0] reserved
Mult [1:0]
NrBytesToTransfer[14:0] (32 kbytes for high-speed)
V
[1] [2]
Reserved. EndPt[0].
Embedded Hi-Speed USB host controller
ISP1760
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
Table 69: Bit DW7 63 to 52 51 to 40 39 to 32 DW6 31 to 28 27 to 16 15 to 4 3 to 0 DW5 63 to 56 55 to 44 43 to 32 DW4 31 to 29 28 to 26 25 to 23 22 to 20 19 to 17 16 to 14 13 to 11 10 to 8
High-speed interrupt IN and OUT, QHP: bit description Symbol INT_IN_7[[11:0] INT_IN_6[11:0] INT_IN_5[7:0] Access HW -- writes HW -- writes HW -- writes Description Bytes received during SOF7, if SA[7] is set to 1 and frame number is correct. Bytes received during SOF6, if SA[6] is set to 1 and frame number is correct. Bytes received during SOF5 (bits 7 to 0), if SA[5] is set to 1 and frame number is correct. Bytes received during SOF5 (bits 3 to 0), if SA[5] is set to 1 and frame number is correct. Bytes received during SOF4, if SA[4] is set to 1 and frame number is correct. Bytes received during SOF3, if SA[3] is set to 1 and frame number is correct. Bytes received during SOF2 (bits 11 to 8), if SA[2] is set to 1 and frame number is correct. Bytes received during SOF2 (bits 7 to 0), if SA[2] is set to 1 and frame number is correct. Bytes received during SOF1, if SA[1] is set to 1 and frame number is correct. Bytes received during SOF0, if SA[0] is set to 1 and frame number is correct. INT OUT or IN Status7[2:0] Status6[2:0] Status5[2:0] Status4[2:0] Status3[2:0] Status2[2:0] Status1[2:0] Status0[2:0] HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes INT IN or OUT status of SOF7 INT IN or OUT status of SOF6 INT IN or OUT status of SOF5 INT IN or OUT status of SOF4 INT IN or OUT status of SOF3 INT IN or OUT status of SOF2 INT IN or OUT status of SOF1 Status of the payload on the USB bus for this SOF after INT has been delivered. Bit 0 -- Transaction Error (IN and OUT) Bit 1 -- Babble (IN token only) Bit 2 -- underrun (OUT token only).
INT_IN_5[3:0] INT_IN_4[11:0] INT_IN_3[11:0] INT_IN_2[3:0]
HW -- writes HW -- writes HW -- writes HW -- writes
INT_IN_2[7:0] INT_IN_1[11:0] INT_IN_0[11:0]
HW -- writes HW -- writes HW -- writes
7 to 0
SA[7:0]
SW -- writes (0 => 1)
When the frame number of bits DW1[7:3] match the frame number of the USB bus, these bits are checked for 1 before they are sent for SOF. For example: When SA[7:0] = 1, 1, 1, 1, 1, 1, 1, 1: send INT for every SOF of HW -- writes the entire ms. When SA[7:0] = 0, 1, 0, 1, 0, 1, 0, 1: send INT for SOF0, (1 => 0) SOF2, SOF4 and SOF6. When SA[7:0] = 1, 0, 0, 0, 1, 0, 0, 0 = send After processing INT for every fourth SOF. HW -- writes SW -- writes Active: Write the same value as that in V.
DW3 63 A
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Embedded Hi-Speed USB host controller
Table 69: Bit 62 61 to 58 57
High-speed interrupt IN and OUT, QHP: bit description...continued Symbol H reserved DT Access HW -- writes HW -- writes SW -- writes Description Halt: Transaction is halted. Data Toggle: Set the Data Toggle bit to start the PTD. Software writes the current transaction toggle value. Hardware writes the next transaction toggle value. Error Counter. This field corresponds to the Cerr[1:0] field in the QH. The default value of this field is zero for isochronous transactions. Number of Bytes Transferred: This field indicates the number of bytes sent or received for this transaction. If Mult[1:0] is greater than one, it is possible to store intermediate results in this field. Data Start Address: This is the start address for the data that will be sent or received on or from the USB bus. This is the internal memory address and not the direct CPU address. RAM address = (CPU address - 400h)/8 Bits 7 to 3 represent the polling rate for ms-based polling. The INT polling rate is defined as 2(b - 1) SOF, where b is 1 to 9. When b is 1, 2, 3 or 4, use SA to define polling because the rate is equal to or less than 1 ms. Bits 7 to 3 are set to 0. Polling checks SA bits for SOF rates. b 1 2 3 4 5 6 7 8 9 rate 1 SOF 2 SOF 4 SOF 1 ms 2 ms 4 ms 8 ms 16 ms 32 ms Frame[7:3] 0 0 0 0 1 10 to 11 100 to 111 1000 to 1111 10000 to 11111 SA[7:0] 11111111 10101010 or 01010101 any 2 bits set any 1 bit set any 1 bit set any 1 bit set any 1 bit set any 1 bit set any 1 bit set
56 to 55 54 to 47 46 to 32
Cerr[1:0] reserved NrBytes Transferred [14:0] reserved DataStart Address [15:0] Frame[7:0]
HW -- writes SW -- writes HW -- writes
DW2 31 to 24 23 to 8 SW -- writes
7 to 0
SW -- writes
DW1 63 to 47 46 reserved S SW -- writes This bit indicates if a split transaction has to be executed: 0 -- High-speed transaction 1 -- Split transaction. 45 to 44 43 to 42 EPType[1:0] Token[1:0] SW -- writes SW -- writes Endpoint type: 11 -- Interrupt. Token: This field indicates the token PID for this transaction: 00 -- OUT 01 -- IN.
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ISP1760
Embedded Hi-Speed USB host controller
Table 69: Bit 41 to 35 34 to 32 DW0 31 30 to 29
High-speed interrupt IN and OUT, QHP: bit description...continued Symbol DeviceAddress [6:0] EndPt[3:1] EndPt[0] Mult[1:0] Access SW -- writes SW -- writes SW -- writes SW -- writes Description Device Address: This is the USB address of the function containing the endpoint that is referred to by the buffer. Endpoint: This is the USB address of the endpoint within the function. Endpoint: This is the USB address of the endpoint within the function. Multiplier: This field is a multiplier counter used by the Host Controller as the number of successive packets the Host Controller may submit to the endpoint in the current execution. Set this field to 01b. You can also set it to 11b and 10b depending on your application. 00b is undefined.
28 to 18
MaxPacket Length[10:0] NrBytesTo Transfer[14:0] reserved V
SW -- writes
Maximum Packet Length: This field indicates the maximum number of bytes that can be sent to or received from the endpoint in a single data packet. Number of Bytes to Transfer: This field indicates the number of bytes can be transferred by this data structure. It is used to indicate the depth of the DATA field (32 kbytes). Valid: 0 -- This bit is deactivated when the entire PTD is executed--across SOF and SOF--or when a fatal error is encountered. 1 -- Software updates to one when there is payload to be sent or received even across ms boundary. The current PTD is active.
17 to 3
SW -- writes
2 to 1 0
SW -- sets HW -- resets
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9.4 Start and complete split for bulk, Queue Head Asynchronous Start Split and Start Complete (QHA-SS/SC) (patent-pending)
Table 70: Bit DW7 DW5 DW3 DW1 A H B X S C
[1]
Product data sheet Rev. 01 -- 8 November 2004 70 of 105
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Start and complete split for bulk, QHASS/SC: bit allocation 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 reserved reserved D T Cerr [1:0] NakCnt[3:0] PortNumber[6:0] reserved SE[1:0]
[1]
63
NrBytesTransferred[14:0] S EP Type [1:0] 13 12 Token [1:0] 11 10 9 DeviceAddress[6:0] EndPt[3:0] (31 to 34) 3 2 1 0
HubAddress[6:0]
Bit DW6 DW4 DW2 DW0
[1] [2]
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
8
7
6
5 J
4
reserved reserved reserved
[2] [1]
NextPTDAddress[4:0] reserved
[1]
RL[3:0]
[1]
DataStartAddress[15:0] NrBytesToTransfer[14:0] (32 kbytes for high-speed)
MaxPacketLength[10:0]
V
Reserved. EndPt[0].
Embedded Hi-Speed USB host controller
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1760
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
Table 71: Bit DW7 63 to 32 DW6 31 to 0 DW5 63 to 32 DW4 31 to 6 5 4 to 0 DW3 63 62 61
Start and complete split for bulk, QHASS/SC: bit description Symbol reserved reserved reserved reserved J NextPTDPointer [1:0] A H B Access SW -- writes SW -- writes Description 0 -- To increment the PTD pointer 1 -- To enable the next PTD branching. Next PTD branching assigned by the PTD pointer.
SW -- sets HW -- resets HW -- writes HW -- writes
Active: Write the same value as that in V. Halt: This bit correspond to the Halt bit of the Status field of QH. Babble: This bit correspond to the Babble Detected bit in the Status field of the iTD, SiTD or QH. 1 -- when babbling is detected, A and V are set to 0. Transaction Error: This bit corresponds to the Transaction Error bit in the status field.
60 59
X SC SW -- writes 0 HW -- updates
Start/Complete: 0 -- Start split 1 -- Complete split. Data Toggle: Set the Data Toggle bit to start for the PTD. Error Counter: This field contains the error count for start and complete split (QHASS). When an error has no response or bad response, Cerr[1:0] will be decremented to zero and then Valid will be set to zero. A NAK or NYET will reset Cerr[1:0]. For details, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 Section 4.12.1.2. If retry has insufficient time at the beginning of a new SOF, the first PTD must be this retry. This can be accomplished by if aperiodic PTD is not advanced.
58 57 56 to 55
reserved DT Cerr[1:0]
HW -- writes SW -- writes HW -- updates SW -- writes
54 to 51 50 to 47 46 to 32 DW2 31 to 29
NakCnt[3:0] reserved
HW -- writes SW -- writes -
NAK Counter. The V bit is reset if NakCnt decrements to zero and RL is a non-zero value. Not applicable to isochronous split transactions. Number of Bytes Transferred: This field indicates the number of bytes sent or received for this transaction. -
NrBytesTransferred HW -- writes [14:0] reserved -
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Embedded Hi-Speed USB host controller
Table 71: Bit 28 to 25
Start and complete split for bulk, QHASS/SC: bit description...continued Symbol RL[3:0] Access SW -- writes Description Reload. If RL is set to 0h, hardware ignores the NakCnt value. Set RL and NakCnt to the same value before a transaction. For full-speed and low-speed transactions, set this field to 0000b. Not applicable to isochronous start split and complete split. Data Start Address: This is the start address for the data that will be sent or received on or from the USB bus. This is the internal memory address and not the direct CPU address. RAM address = (CPU address - 400h)/8 Hub Address: This indicates the hub address. Zero for the internal or embedded hub. Port Number: This indicates the port number of the hub or embedded TT. This depends on the endpoint type and direction. It is valid only for split transactions. The following applies to start split and complete split only. Bulk Control I/O I/O I/O I/O S 1 0 E 0 0 Remarks low-speed full-speed
24 23 to 8
reserved DataStartAddress [15:0]
SW -- writes
7 to 0 DW1 63 to 57 56 to 50 49 to 48
reserved HubAddress[6:0] PortNumber[6:0] SE[1:0]
SW -- writes SW -- writes SW -- writes
47 46
reserved S
SW -- writes
This bit indicates whether a split transaction has to be executed: 0 -- High-speed transaction 1 -- Split transaction.
45 to 44
EPType[1:0]
SW -- writes
Endpoint Type: 00 -- Control 10 -- Bulk.
43 to 42
Token[1:0]
SW -- writes
Token: This field indicates the PID for this transaction. 00 -- OUT 01 -- IN 10 -- SETUP.
41 to 35 34 to 32 DW0 31 30 to 29 28 to 18
DeviceAddress [6:0] EndPt[3:1] EndPt[0] reserved MaximumPacket Length[10:0]
SW -- writes SW -- writes SW -- writes SW -- writes
Device Address: This is the USB address of the function containing the endpoint that is referred to by this buffer. Endpoint: This is the USB address of the endpoint within the function. Endpoint: This is the USB address of the endpoint within the function. Maximum Packet Length: This field indicates the maximum number of bytes that can be sent to or received from an endpoint in a single data packet. The maximum packet size for full-speed is 64 bytes as defined in the Universal Serial Bus Specification Rev. 2.0.
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Embedded Hi-Speed USB host controller
Table 71: Bit 17 to 3
Start and complete split for bulk, QHASS/SC: bit description...continued Symbol NrBytesToTransfer [14:0] reserved V Access SW -- writes Description Number of Bytes to Transfer: This field indicates the number of bytes that can be transferred by this data structure. It is used to indicate the depth of the DATA field. Valid: 0 -- This bit is deactivated when the entire PTD is executed--across SOF and SOF--or when a fatal error is encountered. 1 -- Software updates to one when there is payload to be sent or received even across ms boundary. The current PTD is active.
2 to 1 0
SW -- sets HW -- resets
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9.5 Start and complete split for isochronous, Split isochronous Transfer Descriptor (SiTD) (patent-pending)
Table 72: Bit DW7 DW5 DW3 DW1 A H ISO_IN_2[7:0] B X S C
[1]
Product data sheet Rev. 01 -- 8 November 2004 74 of 105
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Start and complete split for isochronous, SiTD: bit allocation 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 reserved ISO_IN_1[7:0] D T PortNumber[6:0] reserved reserved S EP Type [1:0] 13 12 Token [1:0] 11 10 9 ISO_IN_0[7:0] ISO_IN_7[7:0] SCS[7:0] [2] NrBytesTransferred[11:0] DeviceAddress[6:0] EndPt[3:0] (31 to 34) 3 2 1 0
63
HubAddress[6:0]
Bit DW6 DW4 DW2 DW0
[1] [2] [3]
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
8
7
6
5
4
ISO_IN_6[7:0] Status7 [2:0]
[3] [1]
ISO_IN_5[7:0] Status5 [2:0] Status4 [2:0] Status3 [2:0] Status2 [2:0]
ISO_IN_4[7:0] Status1 [2:0] Status0 [2:0]
ISO_IN_3[7:0] SA[7:0] Frame[7:0] (full-speed)
[1]
Status6 [2:0] reserved
DataStartAddress[15:0] TT_MPS_Len[10:0]
NrBytesToTransfer[14:0] (1 kbyte for full-speed)
V
Reserved. Note the change in the position of USCS[7:0] and NrBytesReceived_CS_IN. EndPt[0].
Embedded Hi-Speed USB host controller
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1760
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
Table 73: Bit DW7 63 to 40 39 to 32 DW6 31 to 24 23 to 16 15 to 8 7 to 0 DW5 63 to 56 55 to 48 47 to 40 39 to 32
Start and complete split for isochronous, SiTD: bit description Symbol reserved ISO_IN_7[7:0] Access HW -- writes Description Bytes received during SOF7, if SA[7] is set to 1 and frame number is correct. Bytes received during SOF6, if SA[6] is set to 1 and frame number is correct. Bytes received during SOF5, if SA[5] is set to 1 and frame number is correct. Bytes received during SOF4, if SA[4] is set to 1 and frame number is correct. Bytes received during SOF3, if SA[3] is set to 1 and frame number is correct. Bytes received during SOF2 (bits 7 to 0), if SA[2] is set to 1 and frame number is correct. Bytes received during SOF1, if SA[1] is set to 1 and frame number is correct. Bytes received during SOF0 if SA[0] is set to 1 and frame number is correct. All bits can be set to one for every transfer. It specifies which SOF the complete split needs to be sent. Valid only for IN. Start split (SS) and complete split (CS) active bits--SA = 0000 0001, S CS = 0000 0100--will cause SS to execute in Frame0 and CS in Frame2.
ISO_IN_6[7:0] ISO_IN_5[7:0] ISO_IN_4[7:0] ISO_IN_3[7:0]
HW -- writes HW -- writes HW -- writes HW -- writes
ISO_IN_2[7:0] ISO_IN_1[7:0] ISO_IN_0[7:0] SCS[7:0]
HW -- writes HW -- writes HW -- writes SW -- writes (0 => 1) HW -- writes (1 => 0) After processing
DW4 31 to 29 28 to 26 25 to 23 22 to 20 19 to 17 16 to 14 13 to 11 10 to 8 Status7[2:0] Status6[2:0] Status5[2:0] Status4[2:0] Status3[2:0] Status2[2:0] Status1[2:0] Status0[2:0] HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes isochronous IN or OUT status of SOF7 isochronous IN or OUT status of SOF6 isochronous IN or OUT status of SOF5 isochronous IN or OUT status of SOF4 isochronous IN or OUT status of SOF3 isochronous IN or OUT status of SOF2 isochronous IN or OUT status of SOF1 isochronous IN or OUT status of SOF0 Bit 0 -- Transaction Error (IN and OUT) Bit 1 -- Babble (IN token only) Bit 2 -- underrun (OUT token only). 7 to 0 SA[7:0] SW -- writes (0 => 1) HW -- writes (1 => 0) After processing Specifies which SOF the start split needs to be placed. For OUT token: When the frame number of bits DW1(7-3) matches the frame number of the USB bus, these bits are checked for one before they are sent for the SOF. For IN token: Only SOF0, SOF1, SOF2 or SOF3 can be set to 1. Nothing can be set for SOF4 and above.
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Embedded Hi-Speed USB host controller
Table 73: Bit DW3 63 62 61 60 59
Start and complete split for isochronous, SiTD: bit description...continued Symbol A H B X SC Access SW -- sets HW -- resets HW -- writes HW -- writes HW -- writes SW -- writes 0 HW -- updates Halt: The Halt bit is set when any microframe transfer status has a stalled or halted condition. Babble: This bit corresponds to bit 1 of Status0 to Status7 for every microframe transfer status. Transaction Error: This bit corresponds to bit 0 of Status0 to Status7 for every microframe transfer status. Start/Complete: 0 -- Start split 1 -- Complete split. Data Toggle: Set the Data Toggle bit to start for the PTD. Number of Bytes Transferred: This field indicates the number of bytes sent or received for this transaction. Data Start Address: This is the start address for the data that will be sent or received on or from the USB bus. This is the internal memory address and not the CPU address. Bits 7 to 3 determine which frame to execute. Hub Address: This indicates the hub address. Zero for the internal or embedded hub. Port Number: This indicates the port number of the hub or embedded TT. This bit indicates whether a split transaction has to be executed: 0 -- High-speed transaction 1 -- Split transaction. Description Active: Write the same value as that in V.
58 57 56 to 44 43 to 32 DW2 31 to 24 23 to 8
reserved DT reserved
HW -- writes SW -- writes -
NrBytesTransferred HW -- writes [11:0] reserved DataStartAddress [15:0] Frame[7:0] HubAddress [6:0] PortNumber [6:0] reserved S SW -- writes
7 to 0 DW1 63 to 57 56 to 50 49 to 47 46
SW -- writes SW -- writes SW -- writes SW -- writes
45 to 44 43 to 42
EPType[1:0] Token[1:0]
SW -- writes SW -- writes
Transaction type: 01 -- Isochronous. Token PID for this transaction: 00 -- OUT 01 -- IN.
41 to 35 34 to 32 DW0 31 30 to 29
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Device Address[6:0] EndPt[3:1] EndPt[0] reserved
SW -- writes SW -- writes SW -- writes -
Device Address: This is the USB address of the function containing the endpoint that is referred to by this buffer. Endpoint: This is the USB address of the endpoint within the function. Endpoint: This is the USB address of the endpoint within the function. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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ISP1760
Embedded Hi-Speed USB host controller
Table 73: Bit 28 to 18
Start and complete split for isochronous, SiTD: bit description...continued Symbol TT_MPS_Len [10:0] Access SW -- writes Description Transaction Translator Maximum Packet Size Length: This field indicates the maximum number of bytes that can be sent per start split depending on the number of total bytes needed. If the total bytes to be sent for the entire ms is greater than 188 bytes, this field should be set to 188 bytes for an OUT token and 192 byes for an IN token. Otherwise, this field should be equal to the total bytes sent. Number of Bytes to Transfer: This field indicates the number of bytes that can be transferred by this data structure. It is used to indicate the depth of the DATA field. This field is restricted to 1023 bytes because in SiTD the maximum allowable payload for a full-speed device is 1023 bytes. This field indirectly becomes the maximum packet size of the downstream device. 0 -- This bit is deactivated when the entire PTD is executed--across SOF and SOF--or when a fatal error is encountered. 1 -- Software updates to one when there is payload to be sent or received even across ms boundary. The current PTD is active.
17 to 3
NrBytesTo Transfer [14:0]
SW -- writes
2 to 1 0
reserved V
SW -- sets HW -- resets
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9.6 Start and complete split for interrupt (patent-pending)
Table 74: Bit DW7 DW5 DW3 DW1 A H INT_IN_2[7:0] B X S C
[1]
Product data sheet Rev. 01 -- 8 November 2004 78 of 105
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Start and complete split for interrupt: bit allocation 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 reserved INT_IN_1[7:0] D T Cerr [1:0] PortNumber[6:0] reserved SE[1:0] S EP Type [1:0] 13 12 INT_IN_0[7:0] INT_IN_7[7:0] SCS[7:0] NrBytesTransferred[11:0] (4 kbytes for full-speed and low-speed) Token [1:0] 11 10 9 DeviceAddress[6:0] EndPt [3:0] 3 2 1 0
63
HubAddress[6:0]
Bit DW6 DW4 DW2 DW0
[1] [2]
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
8
7
6
5
4
INT_IN_6[7:0] Status7 [2:0] Status6 [2:0] reserved
[2] [1]
INT_IN_5[7:0] Status5 [2:0] Status4 [2:0] Status3 [2:0] Status2 [2:0]
INT_IN_4[7:0] Status1 [2:0] Status0 [2:0]
INT_IN_3[7:0] SA[7:0] Frame[7:0] (full-speed and low-speed)
[1]
DataStartAddress[15:0] MaxPacketLength[10:0]
NrBytesToTransfer[14:0] (4 kbytes for full-speed and low-speed)
V
Reserved. EndPt[0].
Embedded Hi-Speed USB host controller
ISP1760
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
Table 75: Bit DW7 63 to 40 39 to 32 DW6 31 to 24 23 to 16 15 to 8 7 to 0 DW5 63 to 56
Start and complete split for interrupt: bit description Symbol reserved INT_IN_7[7:0] Access HW -- writes Description Bytes received during SOF7, if SA[7] is set to 1 and frame number is correct. The new value continuously overwrites the old value. Bytes received during SOF6, if SA[6] is set to 1 and frame number is correct. The new value continuously overwrites the old value. Bytes received during SOF5, if SA[5] is set to 1 and frame number is correct. The new value continuously overwrites the old value. Bytes received during SOF4, if SA[4] is set to 1 and frame number is correct. The new value continuously overwrites the old value. Bytes received during SOF3, if SA[3] is set to 1 and frame number is correct. The new value continuously overwrites the old value. Bytes received during SOF2 (bits 7 to 0), if SA[2] is set to 1 and frame number is correct. The new value continuously overwrites the old value. Bytes received during SOF1, if SA[1] is set to 1 and frame number is correct. The new value continuously overwrites the old value. Bytes received during SOF0 if SA[0] is set to 1 and frame number is correct. The new value continuously overwrites the old value.
INT_IN_6[7:0] INT_IN_5[7:0] INT_IN_4[7:0] INT_IN_3[7:0]
HW -- writes HW -- writes HW -- writes HW -- writes
INT_IN_2[7:0]
HW -- writes
55 to 48 47 to 40 39 to 32
INT_IN_1[7:0] INT_IN_0[7:0] SCS[7:0]
HW -- writes HW -- writes
SW -- writes (0 => 1) All bits can be set to one for every transfer. It specifies which SOF the complete split needs to be sent. Valid only for IN. Start split (SS) and HW -- writes complete split (CS) active bits--SA = 0000 0001, S CS = 0000 (1 => 0) 0100--will cause SS to execute in Frame0 and CS in Frame2. After processing HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes interrupt IN or OUT status of SOF7 interrupt IN or OUT status of SOF6 interrupt IN or OUT status of SOF5 interrupt IN or OUT status of SOF4 interrupt IN or OUT status of SOF3 interrupt IN or OUT status of SOF2 interrupt IN or OUT status of SOF1 interrupt IN or OUT status of SOF0 Bit 0 -- Transaction Error (IN and OUT) Bit 1 -- Babble (IN token only) Bit 2 -- underrun (OUT token only).
DW4 31 to 29 28 to 26 25 to 23 22 to 20 19 to 17 16 to 14 13 to 11 10 to 8 Status7[2:0] Status6[2:0] Status5[2:0] Status4[2:0] Status3[2:0] Status2[2:0] Status1[2:0] Status0[2:0]
7 to 0
SA[7:0]
SW -- writes (0 => 1) Specifies which SOF the start split needs to be placed. HW -- writes (1 => 0) After processing For OUT token: When the frame number of bits DW1(7-3) matches the frame number of the USB bus, these bits are checked for one before they are sent for the SOF. For IN token: Only SOF0, SOF1, SOF2 or SOF3 can be set to 1. Nothing can be set for SOF4 and above.
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Embedded Hi-Speed USB host controller
Table 75: Bit DW3 63 62 61 60 59
Start and complete split for interrupt: bit description...continued Symbol A H B X SC Access SW -- sets HW -- resets HW -- writes HW -- writes HW -- writes SW -- writes 0 HW -- updates Halt: The Halt bit is set when any microframe transfer status has a stalled or halted condition. Babble: This bit corresponds to bit 1 of Status0 to Status7 for every microframe transfer status. Transaction Error: This bit corresponds to bit 0 of Status0 to Status7 for every microframe transfer status. Start/Complete: 0 -- Start split 1 -- Complete split. Data Toggle: For an interrupt transfer, set correct bit to start the PTD. Error Counter. This field corresponds to the Cerr[1:0] field in QH. 00 -- The transaction will not retry. 11 -- The transaction will retry three times. Hardware will decrement these values. When the transaction has tried three times, X error will be updated. Description Active: Write the same value as that in V.
58 57 56 to 55
reserved DT Cerr[1:0]
HW -- writes SW -- writes HW -- writes SW -- writes
54 to 44 43 to 32
reserved NrBytes Transferred [11:0] reserved DataStart Address[15:0] Frame[7:0]
HW -- writes
Number of Bytes Transferred: This field indicates the number of bytes sent or received for this transaction.
DW2 31 to 24 23 to 8 SW -- writes Data Start Address: This is the start address for the data that will be sent or received on or from the USB bus. This is the internal memory address and not the CPU address. Bits 7 to 3 is the ms polling rate. Polling rate is defined as 2(b - 1) SOF; where b = 4 to 16. When b is 4, every ms is executed. b 4 5 6 7 DW1 63 to 57 56 to 50 HubAddress [6:0] PortNumber [6:0] SW -- writes SW -- writes Hub Address: This indicates the hub address. Zero for the internal or embedded hub. Port Number: This indicates the port number of the hub or embedded TT. Rate 2 4 8 16 Bits 7 to 3 00001 00010 or 00011 00100 or 00101 01000 or 01001 up to 32 ms
7 to 0
SW -- writes
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ISP1760
Embedded Hi-Speed USB host controller
Table 75: Bit 49 to 48
Start and complete split for interrupt: bit description...continued Symbol SE[1:0] Access SW -- writes Description This depends on the endpoint type and direction. It is valid only for split transactions. The following applies to start split and complete split only. Interrupt I/O I/O S 1 0 E 0 0 Remarks low-speed full-speed
47 46
reserved S
SW -- writes
This bit indicates whether a split transaction has to be executed: 0 -- High-speed transaction 1 -- Split transaction.
45 to 44 43 to 42
EPType[1:0] Token[1:0]
SW -- writes SW -- writes
Transaction type: 11 -- Interrupt. Token PID for this transaction: 00 -- OUT 01 -- IN.
41 to 35 34 to 32 DW0 31 30 to 29 28 to 18
DeviceAddress [6:0] EndPt[3:1] EndPt[0] reserved MaxPacket Length[10:0]
SW -- writes SW -- writes SW -- writes SW -- writes
Device Address: This is the USB address of the function containing the endpoint that is referred to by this buffer. Endpoint: This is the USB address of the endpoint within the function. Endpoint: This is the USB address of the endpoint within the function. Maximum Packet Length: This field indicates the maximum number of bytes that can be sent to or received from an endpoint in a single data packet. The maximum packet size for the full-speed and low-speed devices is 64 bytes as defined in the Universal Serial Bus Specification Rev. 2.0. Number of Bytes to Transfer: This field indicates the number of bytes that can be transferred by this data structure. It is used to indicate the depth of the DATA field. The maximum total number of bytes for this transaction is 4 kbytes. 0 -- This bit is deactivated when the entire PTD is executed--across SOF and SOF--or when a fatal error is encountered. 1 -- Software updates to one when there is payload to be sent or received even across ms boundary. The current PTD is active.
17 to 3
NrBytesTo Transfer[14:0]
SW -- writes
2 to 1 0
reserved V
SW -- sets HW -- resets
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10. Power consumption
Table 76: Power consumption ICC 90 mA 77 mA 82 mA 77 mA 110 mA 97 mA 102 mA 97 mA 130 mA 117 mA 122 mA 117 mA ICC(I/O) <10 A <10 A <10 A <10 A <10 A <10 A <10 A <10 A <10 A <10 A <10 A <10 A Number of ports working One port working (high-speed) VCC = 5.0 V, VCC(I/O) = 3.3 V VCC = 3.3 V, VCC(I/O) = 3.3 V VCC = 5.0 V, VCC(I/O) = 1.8 V VCC = 3.3 V, VCC(I/O) = 1.8 V Two ports working (high-speed) VCC = 5.0 V, VCC(I/O) = 3.3 V VCC = 3.3 V, VCC(I/O) = 3.3 V VCC = 5.0 V, VCC(I/O) = 1.8 V VCC = 3.3 V, VCC(I/O) = 1.8 V Three ports working (high-speed) VCC = 5.0 V, VCC(I/O) = 3.3 V VCC = 3.3 V, VCC(I/O) = 3.3 V VCC = 5.0 V, VCC(I/O) = 1.8 V VCC = 3.3 V, VCC(I/O) = 1.8 V
Remark: The idle operating current, that is, when the ISP1760 is in operational mode--initialized and without any devices connected, is 70 mA. The additional current consumption on ICC is below 1 mA per port in the case of full-speed and low-speed devices. Remark: Deep-sleep suspend mode ensures the lowest power consumption when VCC is always supplied to the ISP1760. In this case, the suspend current is typically about 100 A at room temperature. The suspend current may increase if the ambient temperature increases. For details, see Section 7.6. Remark: In hybrid mode, when VCC is disconnected ICC(I/O) will be generally below 100 A. The average value is 60 A to 70 A.
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11. Limiting values
Table 77: Absolute maximum ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC(I/O) VCC(5V0) Ilu Vesd Tstg Parameter supply voltage supply voltage latch-up current electrostatic discharge voltage storage temperature VI < 0 or VI > VCC ILI < 1 A Conditions Min -0.5 -0.5 -4000 -40 Max +3.6 +5.5 100 +4000 +125 Unit V V mA V C
12. Recommended operating conditions
Table 78: Symbol VCC(I/O) VCC(5V0) Tamb Recommended operating conditions Parameter supply voltage supply voltage operating temperature Conditions VCC(I/O) = 3.3 V VCC(I/O) = 1.8 V Min 3.0 1.65 3.0 -40 Typ 3.3 1.8 Max 3.6 1.95 5.5 +85 Unit V V V C
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13. Static characteristics
Table 79: Static characteristics: digital pins Digital pins: A[17:1], DATA[31:0], CS_N, RD_N, WR_N, DACK, DREQ, IRQ, RESET_N, SUSPEND/WAKEUP_N, CLKIN, OC1_N, OC2_N, OC3_N. OC1_N, OC2_N and OC3_N are used as digital overcurrent pins; VCC(I/O) = 3.0 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified Symbol VIH VIL Vhys VOL VOH IIL CIN Parameter HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage HIGH-level output voltage input leakage current input pin capacitance 0 < VIN Table 80: Static characteristics: digital pins Digital pins: A[17:1], DATA[31:0], CS_N, RD_N, WR_N, DACK, DREQ, IRQ, RESET_N, SUSPEND/WAKEUP_N, CLKIN, OC1_N, OC2_N, OC3_N. OC1_N, OC2_N and OC3_N are used as digital overcurrent pins; VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol VIH VIL Vhys VOL VOH IIL CIN Parameter HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage HIGH-level output voltage input leakage current input pin capacitance 0 < VIN Table 81: Static characteristics: PSW1_N, PSW2_N, PSW3_N VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol VOL VOH Parameter LOW-level output voltage Conditions IOL = 8 mA, pull-up to VCC(5V0) Min Typ VCC(I/O) Max 0.4 Unit V V
HIGH-level output voltage pull-up to VCC(I/O)
Table 82: Static characteristics: USB interface block (pins DM1 to DM3 and DP1 to DP3) VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol VHSSQ VHSDSC VHSCM Parameter squelch detection threshold (differential signal amplitude) disconnect detection threshold (differential signal amplitude) data signaling common mode voltage range Conditions squelch detected no squelch detected disconnect detected disconnect not detected Min 150 625 -50 Typ Max 100 525 +500 Unit mV mV mV mV mV Input levels for high-speed
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Table 82: Static characteristics: USB interface block (pins DM1 to DM3 and DP1 to DP3)...continued VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol VHSOI VHSOH VHSOL VCHIRPJ VCHIRPK Parameter idle state data signaling HIGH data signaling LOW Chirp J level (differential voltage) Chirp K level (differential voltage) HIGH-level input voltage (drive) HIGH-level input voltage (floating) LOW-level input voltage differential input sensitivity differential common mode range HIGH-level output voltage LOW-level output voltage SEI output signal crossover point voltage |VDP - VDM| Conditions Min -10 360 -10 700 [1] -900 [1] Typ Max +10 440 +10 1100 -500 Unit mV mV mV mV mV Output levels for high-speed
Input levels for full-speed and low-speed VIH VIHZ VIL VDI VCM VOH VOL VOSEI VCRS 2.0 2.7 0.2 0.8 2.8 0 0.8 1.3 3.6 0.8 2.5 3.6 0.3 2.0 V V V V V V V V V
Output levels for full-speed and low-speed
[1]
The HS termination resistor is disabled, and the pull-up resistor is connected. Only during reset, when both the hub and the device are capable of the high-speed operation.
Table 83: Static characteristics: REF5V VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol VIH Parameter HIGH-level input voltage Conditions Min Typ 5 Max Unit V
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14. Dynamic characteristics
Table 84: Dynamic characteristics: system clock timing Conditions crystal [2] oscillator External clock input J Vclk tCR, tCF
[1] [2]
Symbol Parameter Crystal oscillator fclk clock frequency [1]
Min -
Typ 12 12 50 1.8 -
Max 500 3
Unit MHz MHz ps % V ns
external clock jitter clock duty cycle amplitude rise time and fall time
Recommended accuracy of the clock frequency is 50 ppm for the crystal and oscillator. The oscillator used depends on VCC(I/O). Recommended values for external capacitors when using a crystal are 22 pF to 27 pF.
Table 85: Dynamic characteristics: CPU interface block VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol SR Parameter output slew rate (rise, fall) Conditions standard load Min 1 Typ Max 4 Unit V/ns
Table 86: Dynamic characteristics: high-speed source electrical characteristics VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Driver characteristics tHSR tHSF ZHSDRV high-speed differential rise time high-speed differential fall time drive output resistance (this also serves as a high-speed termination) data rate microframe interval consecutive microframe interval difference 10 % to 90 % 90 % to 10 % includes the RS resistor 500 500 40.5 45 49.5 ps ps Conditions Min Typ Max Unit
Clock timing tHSDRAT tHSFRAM tHSRFI 479.76 124.9375 1 480.24 125.0625 four high-speed bit times Mbit/s s ns
Table 87: Dynamic characteristics: full-speed source electrical characteristics VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tFR tFF tFRFM
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Parameter rise time fall time differential rise and fall time matching
Conditions CL = 50 pF; 10 % to 90 % of |VOH - VOL| CL = 50 pF; 90 % to 10 % of |VOH - VOL|
Min 4 4 90
Typ -
Max 20 20 111.1
Unit ns ns %
Driver characteristics
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Table 87: Dynamic characteristics: full-speed source electrical characteristics...continued VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol ZDRV Parameter driver output resistance for the driver that is not high-speed capable source jitter for differential full-speed timing transition to SEO transition source SE0 interval of EOP receiver SE0 interval of EOP source jitter for differential low-speed timing transition to SEO transition source SE0 interval of EOP receiver SE0 interval of EOP width of SE0 interval during differential transaction Conditions Min 28 Typ Max 44 Unit
Data timing: see Figure 11 tFDEOP tFEOPT tFEOPR tLDEOP tLEOPT tLEOPR tFST -2 160 82 -40 1.25 670 +5 175 +100 1.5 14 ns ns ns ns s ns ns
Table 88: Dynamic characteristics: low-speed source electrical characteristics VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tLR tLF tLRFM Parameter rise time fall time differential rise and fall time matching Conditions Min 75 75 90 Typ Max 300 300 125 Unit ns ns % Driver characteristics
TPERIOD +3.3 V crossover point differential data lines crossover point extended
0V differential data to SE0/EOP skew N x TPERIOD + t DEOP source EOP width: t EOPT receiver EOP width: t EOPR
mgr776
TPERIOD is the bit duration corresponding with the USB data rate. Full-speed timing symbols have a subscript prefix `F', low-speed timing symbols have a prefix `L'.
Fig 11. USB source differential data-to-EOP transition skew and EOP width.
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14.1 PIO timing
14.1.1 Register or memory write
th31 A[17:1] address 01 tsu21 CS_N tsu31 WR_N tsu11 DATA data 01 Tcy11 data 02
004aaa527
address 02 th21
tw11 th11
Fig 12. Register or memory write. Table 89: Register or memory write VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol th11 th21 th31 tw11 Tcy11 tsu11 tsu21 tsu31 Parameter data hold after WR_N HIGH CS_N hold after WR_N HIGH address hold after WR_N HIGH WR_N pulse width WR_N to WR_N cycle time data set up time before WR_N HIGH address set up time before WR_N HIGH CS_N set up time before WR_N HIGH Min 2 1 2 17 36 5 5 5 Max Unit ns ns ns ns ns ns ns ns
Table 90: Register or memory write VCC(I/O) = 3.3 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol th11 th21 th31 tw11 Tcy11 tsu11 tsu21 tsu31 Parameter data hold after WR_N HIGH CS_N hold after WR_N HIGH address hold after WR_N HIGH WR_N pulse width WR_N to WR_N cycle time data set up time before WR_N HIGH address set up time before WR_N HIGH CS_N set up time before WR_N HIGH Min 2 1 2 17 36 5 5 5 Max Unit ns ns ns ns ns ns ns ns
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14.1.2 Register read
tsu12 A[17:1] tsu22 CS_N td22 tw12 RD_N Tcy12 DATA
004aaa524
address 01
address 02
td12
Fig 13. Register read. Table 91: Register read VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tsu12 tsu22 tw12 td12 td22 Tcy12 Parameter address set up time before RD_N LOW CS_N set up time before RD_N LOW RD_N pulse width data valid time after RD_N LOW data valid time after RD_N HIGH read-to-read cycle time Min 0 0 td12 40 Max 35 1 Unit ns ns ns ns ns ns
Table 92: Register read VCC(I/O) = 3.3 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tsu12 tsu22 tw12 td12 td22 Tcy12 Parameter address set up time before RD_N LOW CS_N set up time before RD_N LOW RD_N pulse width data valid time after RD_N LOW data valid time after RD_N HIGH read-to-read cycle time Min 0 0 td12 36 Max 22 1 Unit ns ns ns ns ns ns
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14.1.3 Memory read
A[17:1]
address = 33C
address 1 tsu23
address 2
address 3
DATA
data
data 1
data 2
data 3
CS_N td13 WR_N tp13 td23
RD_N Tcy13 tw13
004aaa523
tsu13
Fig 14. Memory read. Table 93: Memory read VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tp13 Tcy13 td13 td23 tw13 tsu13 tsu23 Parameter initial prefetch time memory RD_N cycle time data valid time after RD_N LOW data available time after RD_N HIGH RD_N pulse width CS_N setup time before RD_N LOW address setup time before RD_N LOW Min 90 40 td13 0 0 Max 31 1 Unit ns ns ns ns ns ns ns
Table 94: Memory read VCC(I/O) = 3.3 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tp13 Tcy13 td13 td23 tw13 tsu13 tsu23 Parameter initial prefetch time memory RD_N cycle time data valid time after RD_N LOW data available time after RD_N HIGH RD_N pulse width CS_N setup time before RD_N LOW address setup time before RD_N LOW Min 90 36 td13 0 0 Max 20 1 Unit ns ns ns ns ns ns ns
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14.2 DMA timing
In the following sections:
* Polarity of DACK is active HIGH * Polarity of DREQ is active HIGH.
14.2.1 Single cycle: DMA read
ta44 DREQ ta14 DACK tw14 RD_N ta24 DATA
004aaa530
ta34
td14
Fig 15. DMA read (single cycle). Table 95: DMA read (single cycle) VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol ta14 ta24 td14 tw14 ta34 ta44 Parameter DACK assertion time after DREQ assertion RD_N assertion time after DACK assertion data valid time after RD_N assertion RD_N pulse width DREQ deassertion time after RD_N assertion Min 0 0 td14 23 Max 24 56 Unit ns ns ns ns ns ns
DREQ deassertion to next DREQ assertion time -
Table 96: DMA read (single cycle) VCC(I/O) = 3.3 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol ta14 ta24 td14 tw14 ta34 ta44 Parameter DACK assertion time after DREQ assertion RD_N assertion time after DACK assertion data valid time after RD_N assertion RD_N pulse width DREQ deassertion time after RD_N assertion Min 0 0 td14 11 Max 20 56 Unit ns ns ns ns ns ns
DREQ deassertion to next DREQ assertion time -
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14.2.2 Single cycle: DMA write
tcy15 DREQ ta15 DACK ta25 tsu15 WR_N th15 DATA data data 1
004aaa525
ta35 tw15 th25
DREQ and DACK are active HIGH.
Fig 16. DMA write (single cycle). Table 97: DMA write (single cycle) VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter ta15 ta25 th15 th25 tsu15 ta35 tcy15 tw15 DACK assertion time after DREQ assertion WR_N assertion time after DACK assertion data hold time after WR_N deassertion DACK hold time after WR_N deassertion data set-up time before WR_N deassertion DREQ deassertion time after WR_N assertion last DACK strobe deassertion to next DREQ assertion time WR_N pulse width Min 0 1 3 0 5.5 22 82 22 Max Unit ns ns ns ns ns ns ns ns
Table 98: DMA write (single cycle) VCC(I/O) = 3.3 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter ta15 ta25 th15 th25 tsu15 ta35 tcy15 tw15 DACK assertion time after DREQ assertion WR_N assertion time after DACK assertion data hold time after WR_N deassertion DACK hold time after WR_N deassertion data set-up time before WR_N deassertion DREQ deassertion time after WR_N assertion last DACK strobe deassertion to next DREQ assertion time WR_N pulse width Min 0 1 2 0 5.5 8.9 82 22 Max Unit ns ns ns ns ns ns ns ns
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14.2.3 Multicycle: DMA read
ta36 DREQ ta16 DACK ta26 RD_N tw16 td16 DATA data 0 data 1 data n-1 data n Tcy16
ta46
004aaa531
DREQ and DACK are active HIGH.
Fig 17. DMA read (multicycle burst). Table 99: DMA read (multicycle burst) VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter ta16 ta26 td16 tw16 Tcy16 ta36 ta46 DACK assertion after DREQ assertion time RD_N assertion after DACK assertion time data valid time after RD_N assertion RD_N pulse width read-to-read cycle time DREQ deassertion time after last burst RD_N deassertion Min 0 0 td16 40 20 Max 31 82 Unit ns ns ns ns ns ns ns
DACK deassertion to next DREQ assertion time -
Table 100: DMA read (multicycle burst) VCC(I/O) = 3.3 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter ta16 ta26 td16 tw16 Tcy16 ta36 ta46 DACK assertion after DREQ assertion time RD_N assertion after DACK assertion time data valid time after RD_N assertion RD_N pulse width read-to-read cycle time DREQ deassertion time after last burst RD_N deassertion Min 0 0 td16 36 11 Max 16 82 Unit ns ns ns ns ns ns ns
DACK deassertion to next DREQ assertion time -
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14.2.4 Multicycle: DMA write
ta57 DREQ ta17 th27 DACK tsu17 Tcy17 tw17 WR_N ta27 ta47 th17 DATA data 1 data 2 data n-1 data n 004aaa526 ta37
Fig 18. DMA write (multicycle burst). Table 101: DMA write (multicycle burst) VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Tcy17 tsu17 th17 ta17 ta27 ta37 th27 ta47 tw17 ta57 DMA write cycle time data setup time before WR_N deassertion data hold time after WR_N deassertion DACK assertion time after DREQ assertion WR_N assertion time after DACK assertion DREQ deassertion time at last strobe (WR_N) assertion DACK hold time after WR_N deassertion strobe deassertion to next strobe assertion time WR_N pulse width DACK deassertion to next DREQ assertion time Min 51 5 2 0 2 20 0 34 17 Max 82 Unit ns ns ns ns ns ns ns ns ns ns
Table 102: DMA write (multicycle burst) VCC(I/O) = 3.3 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Tcy17 tsu17 th17 ta17 ta27 ta37 th27 ta47 tw17 ta57 DMA write cycle time data setup time before WR_N deassertion data hold time after WR_N deassertion DACK assertion time after DREQ assertion WR_N assertion time after DACK assertion DREQ deassertion time at last strobe (WR_N) assertion DACK hold time after WR_N deassertion strobe deassertion to next strobe assertion time WR_N pulse width DACK deassertion to next DREQ assertion time Min 51 5 2 0 1 0 0 34 17 Max 82 Unit ns ns ns ns ns ns ns ns ns ns
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15. Package outline
LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm SOT425-1
c
y X
A 102 103 65 64 ZE
e E HE A A2 A 1
(A 3) Lp L detail X
wM pin 1 index 128 1 wM D HD ZD B vM B 39 38 bp vM A bp
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D(1) Z E(1) 0.81 0.59 0.81 0.59 7o o 0
22.15 16.15 21.85 15.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT425-1 REFERENCES IEC 136E28 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-20
Fig 19. Package outline (LQFP128).
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16. Soldering
16.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
16.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
16.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
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- smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
16.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
16.5 Package related soldering information
Table 103: Suitability of surface mount IC packages for wave and reflow soldering methods Package [1] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, USON, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8], PMFP [9], WQCCN..L [8]
[1] [2]
Soldering method Wave not suitable not suitable [4] Reflow [2] suitable suitable
suitable not not recommended [5] [6] recommended [7]
suitable suitable suitable not suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[3]
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Embedded Hi-Speed USB host controller
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[5] [6] [7] [8]
[9]
17. Abbreviations
Table 104: Abbreviations Acronym ATL DMA DSC EHCI EMI FS HC HS INT ISO iTD ITL LS OHCI PDA PLL PIO PTD QHA QHP QHA-SS/SC SiTD TT UHCI USB Description Acknowledged Transfer List Direct Memory Access Digital Still Camera Enhanced Host Controller Interface Electro-Magnetic Interference full-speed Host Controller high-speed INTerrupt isochronous isochronous Transfer Descriptor Isochronous (ISO) Transfer List low-speed Open Host Controller Interface Personal Digital Assistant Phase-Locked Loop Programmed Input/Output Philips Transfer Descriptor Queue Head Asynchronous Queue Head Periodic Queue Head Asynchronous-Start Split/Start Complete Split isochronous Transfer Descriptor Transaction Translator Universal Host Controller Interface Universal Serial Bus
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Product data sheet
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ISP1760
Embedded Hi-Speed USB host controller
18. References
[1] [2] [3] [4] [5] [6]
Universal Serial Bus Specification Rev. 2.0 Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 On-The-Go Supplement to the USB Specification Rev. 1.0a Embedded Systems Design with the ISP176x (AN10043) ISP176x Linux Programming Guide (AN10042) Interfacing the ISP76x to the Intel(R) PXA250 Processor (AN10037).
19. Revision history
Table 105: Revision history Document ID ISP1760_1 Release date 20041108 Data sheet status Product data sheet Change notice Doc. number 9397 750 13257 Supersedes -
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Embedded Hi-Speed USB host controller
20. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
21. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
23. Trademarks
Intel -- is a registered trademark of Intel Corporation.
22. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
24. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
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ISP1760
Embedded Hi-Speed USB host controller
25. Tables
Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Table 28: Table 29: Table 30: Table 31: Table 32: Table 33: Table 34: Table 35: Table 36: Table 37: Table 38: Table 39: Table 40: Table 41: Table 42: Table 43: Table 44: Table 45: Table 46: Table 47: Ordering information . . . . . . . . . . . . . . . . . . . . .3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Memory address . . . . . . . . . . . . . . . . . . . . . . .15 Using the IRQ Mask AND or IRQ Mask OR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Register overview . . . . . . . . . . . . . . . . . . . . . .27 CAPLENGTH register: bit description . . . . . . .28 HCIVERSION register: bit description . . . . . . .28 HCSPARAMS register: bit allocation . . . . . . . .28 HCSPARAMS register: bit description . . . . . . .29 HCCPARAMS register: bit allocation . . . . . . . .29 HCCPARAMS register: bit description . . . . . . .30 USBCMD register: bit allocation . . . . . . . . . . .31 USBCMD register: bit description . . . . . . . . . .31 USBSTS register: bit allocation . . . . . . . . . . . .32 USBSTS register: bit description . . . . . . . . . . .32 USBINTR register: bit allocation . . . . . . . . . . .32 USBINTR register: bit description . . . . . . . . . .33 FRINDEX register: bit allocation . . . . . . . . . . .33 FRINDEX register: bit description . . . . . . . . . .34 CONFIGFLAG register: bit allocation . . . . . . .34 CONFIGFLAG register: bit description . . . . . .35 PORTSC1 register: bit allocation . . . . . . . . . . .35 PORTSC1 register: bit description . . . . . . . . . .36 ISO PTD Done Map register: bit description . .37 ISO PTD Skip Map register: bit description . . .37 ISO PTD Last PTD register: bit description . . .37 INT PTD Done Map register: bit description . .37 INT PTD Skip Map register: bit description . . .38 INT PTD Last PTD register: bit description . . .38 ATL PTD Done Map register: bit description . .38 ATL PTD Skip Map register: bit description . . .39 ATL PTD Last PTD register: bit description . . .39 HW Mode Control register: bit allocation . . . . .39 HW Mode Control register: bit description . . . .40 Chip ID register: bit description . . . . . . . . . . . .41 Scratch register: bit description . . . . . . . . . . . .41 SW Reset register: bit allocation . . . . . . . . . . .41 SW Reset register: bit description . . . . . . . . . .42 DMA Configuration register: bit allocation . . . .42 DMA Configuration register: bit description . . .43 Buffer Status register: bit allocation . . . . . . . . .43 Buffer Status register: bit description . . . . . . . .44 ATL Done Timeout register: bit description . . .44 Memory register: bit allocation . . . . . . . . . . . . .44 Memory register: bit description . . . . . . . . . . .45 Edge Interrupt Count register: bit allocation . .45 Edge Interrupt Count register: bit description .46 Table 48: Table 49: Table 50: Table 51: Table 52: Table 53: Table 54: Table 55: Table 56: Table 57: Table 58: Table 59: Table 60: Table 61: Table 62: Table 63: Table 64: Table 65: Table 66: Table 67: Table 68: Table 69: Table 70: Table 71: Table 72: Table 73: Table 74: Table 75: Table 76: Table 77: Table 78: Table 79: Table 80: Table 81: Table 82: DMA Start Address register: bit allocation . . . 46 DMA Start Address register: bit description . . 46 Power Down Control register: bit allocation . . 47 Power Down Control register: bit description . 47 Port 1 Control register: bit allocation . . . . . . . . 49 Port 1 Control register: bit description . . . . . . . 49 Interrupt register: bit allocation . . . . . . . . . . . . 50 Interrupt register: bit description . . . . . . . . . . . 50 Interrupt Enable register: bit allocation . . . . . . 51 Interrupt Enable register: bit description . . . . . 52 ISO IRQ Mask OR register: bit description . . . 53 INT IRQ Mask OR register: bit description . . . 53 ATL IRQ Mask OR register: bit description . . . 54 ISO IRQ Mask AND register: bit description . . 54 INT IRQ Mask AND register: bit description . . 54 ATL IRQ Mask AND register: bit description . . 55 High-speed bulk IN and OUT, QHA: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 High-speed bulk IN and OUT, QHA: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 High-speed isochronous IN and OUT, iTD: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 High-speed isochronous IN and OUT, iTD: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 High-speed interrupt IN and OUT, QHP: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 High-speed interrupt IN and OUT, QHP: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Start and complete split for bulk, QHASS/SC: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Start and complete split for bulk, QHASS/SC: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Start and complete split for isochronous, SiTD: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Start and complete split for isochronous, SiTD: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Start and complete split for interrupt: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Start and complete split for interrupt: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Power consumption . . . . . . . . . . . . . . . . . . . . . 82 Absolute maximum ratings . . . . . . . . . . . . . . . 83 Recommended operating conditions . . . . . . . . 83 Static characteristics: digital pins . . . . . . . . . . 84 Static characteristics: digital pins . . . . . . . . . . 84 Static characteristics: PSW1_N, PSW2_N, PSW3_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Static characteristics: USB interface block (pins
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ISP1760
Embedded Hi-Speed USB host controller
DM1 to DM3 and DP1 to DP3) . . . . . . . . . . . .84 Static characteristics: REF5V . . . . . . . . . . . . .85 Dynamic characteristics: system clock timing .86 Dynamic characteristics: CPU interface block .86 Dynamic characteristics: high-speed source electrical characteristics . . . . . . . . . . . . . . . . .86 Table 87: Dynamic characteristics: full-speed source electrical characteristics . . . . . . . . . . . . . . . . .86 Table 88: Dynamic characteristics: low-speed source electrical characteristics . . . . . . . . . . . . . . . . .87 Table 89: Register or memory write . . . . . . . . . . . . . . . .88 Table 90: Register or memory write . . . . . . . . . . . . . . . .88 Table 91: Register read . . . . . . . . . . . . . . . . . . . . . . . . . .89 Table 92: Register read . . . . . . . . . . . . . . . . . . . . . . . . . .89 Table 93: Memory read . . . . . . . . . . . . . . . . . . . . . . . . . .90 Table 94: Memory read . . . . . . . . . . . . . . . . . . . . . . . . . .90 Table 95: DMA read (single cycle) . . . . . . . . . . . . . . . . . .91 Table 96: DMA read (single cycle) . . . . . . . . . . . . . . . . . .91 Table 97: DMA write (single cycle) . . . . . . . . . . . . . . . . .92 Table 98: DMA write (single cycle) . . . . . . . . . . . . . . . . .92 Table 99: DMA read (multicycle burst) . . . . . . . . . . . . . .93 Table 100:DMA read (multicycle burst) . . . . . . . . . . . . . .93 Table 101:DMA write (multicycle burst) . . . . . . . . . . . . . .94 Table 102:DMA write (multicycle burst) . . . . . . . . . . . . . .94 Table 103:Suitability of surface mount IC packages for wave and reflow soldering methods . . . . . . . . . . . . .97 Table 104:Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .98 Table 105:Revision history . . . . . . . . . . . . . . . . . . . . . . . .99 Table 83: Table 84: Table 85: Table 86:
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Embedded Hi-Speed USB host controller
26. Figures
Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin configuration (LQFP128). . . . . . . . . . . . . . . . .5 Internal hub. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Memory segmentation and access block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Adjusting analog overcurrent detection limit (optional). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 ISP1760 power supply connection. . . . . . . . . . . .24 Most commonly used power supply connection. .25 Internal power-on reset timing. . . . . . . . . . . . . . .25 Clock with respect to the external power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 NextPTD traversal rule. . . . . . . . . . . . . . . . . . . . .57 USB source differential data-to-EOP transition skew and EOP width. . . . . . . . . . . . . . . . . . . . . . . . . . .87 Register or memory write. . . . . . . . . . . . . . . . . . .88 Register read. . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Memory read.. . . . . . . . . . . . . . . . . . . . . . . . . . . .90 DMA read (single cycle). . . . . . . . . . . . . . . . . . . .91 DMA write (single cycle). . . . . . . . . . . . . . . . . . . .92 DMA read (multicycle burst). . . . . . . . . . . . . . . . .93 DMA write (multicycle burst). . . . . . . . . . . . . . . . .94 Package outline (LQFP128). . . . . . . . . . . . . . . . .95
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Embedded Hi-Speed USB host controller
27. Contents
1 2 3 3.1 4 5 6 6.1 6.2 7 7.1 7.2 7.2.1 7.2.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4 7.5 7.6 7.7 7.8 7.9 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.2.9 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Examples of a multitude of possible applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . 12 ISP1760 internal architecture: Advanced Philips Slave Host Controller and hub . . . . . . . . . . . . 12 Host Controller buffer memory block . . . . . . . 13 General considerations. . . . . . . . . . . . . . . . . . 13 Structure of the ISP1760 Host Controller memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Accessing the ISP1760 Host Controller memory: PIO and DMA . . . . . . . . . . . . . . . . . . . . . . . . . 16 PIO mode access--memory read cycle . . . . . 17 PIO mode access--memory write cycle. . . . . 17 PIO mode access--register read cycle . . . . . 18 PIO mode access--register write cycle . . . . . 18 DMA--read and write operations . . . . . . . . . . 18 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Phase-Locked Loop (PLL) clock multiplier . . . 21 Power management . . . . . . . . . . . . . . . . . . . . 22 Overcurrent detection . . . . . . . . . . . . . . . . . . . 23 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power-on reset (POR) . . . . . . . . . . . . . . . . . . 25 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 EHCI capability registers . . . . . . . . . . . . . . . . 28 CAPLENGTH register (R: 0000h). . . . . . . . . . 28 HCIVERSION register (R: 0002h) . . . . . . . . . 28 HCSPARAMS register (R: 0004h) . . . . . . . . . 28 HCCPARAMS register (R: 0008h) . . . . . . . . . 29 EHCI operational registers . . . . . . . . . . . . . . . 30 USBCMD register (R/W: 0020h). . . . . . . . . . . 30 USBSTS register (R/W: 0024h) . . . . . . . . . . . 31 USBINTR register (R/W: 0028h). . . . . . . . . . . 32 FRINDEX register (R/W: 002Ch) . . . . . . . . . . 33 CTRLDSSEGMENT register (R/W: 0030h) . . 34 CONFIGFLAG register (R/W: 0060h) . . . . . . . 34 PORTSC1 register (R/W: 0064h) . . . . . . . . . . 35 ISO PTD Done Map register (R: 0130h). . . . . 36 ISO PTD Skip Map register (R/W: 0134h) . . . 37 8.2.10 ISO PTD Last PTD register (R/W: 0138h) . . . 37 8.2.11 INT PTD Done Map register (R: 0140h). . . . . 37 8.2.12 INT PTD Skip Map register (R/W: 0144h) . . . 38 8.2.13 INT PTD Last PTD register (R/W: 0148h) . . . 38 8.2.14 ATL PTD Done Map register (R: 0150h) . . . . 38 8.2.15 ATL PTD Skip Map register (R/W: 0154h) . . . 38 8.2.16 ATL PTD Last PTD register (R/W: 0158h) . . . 39 8.3 Configuration registers . . . . . . . . . . . . . . . . . . 39 8.3.1 HW Mode Control register (R/W: 0300h) . . . . 39 8.3.2 Chip ID register (R: 0304h) . . . . . . . . . . . . . . 41 8.3.3 Scratch register (R/W: 0308h) . . . . . . . . . . . . 41 8.3.4 SW Reset register (R/W: 030Ch) . . . . . . . . . . 41 8.3.5 DMA Configuration register (R/W: 0330h) . . . 42 8.3.6 Buffer Status register (R/W: 0334h) . . . . . . . . 43 8.3.7 ATL Done Timeout register (R/W: 0338h) . . . 44 8.3.8 Memory register (R/W: 033Ch) . . . . . . . . . . . 44 8.3.9 Edge Interrupt Count register (R/W: 0340h) . 45 8.3.10 DMA Start Address register (W: 0344h) . . . . 46 8.3.11 Power Down Control register (R/W: 0354h) . . 46 8.3.12 Port 1 Control register (R/W: 0374h) . . . . . . . 48 8.4 Interrupt registers . . . . . . . . . . . . . . . . . . . . . . 50 8.4.1 Interrupt register (R/W: 0310h) . . . . . . . . . . . 50 8.4.2 Interrupt Enable register (R/W: 0314h) . . . . . 51 8.4.3 ISO IRQ Mask OR register (R/W: 0318h) . . . 53 8.4.4 INT IRQ Mask OR register (R/W: 031Ch) . . . 53 8.4.5 ATL IRQ Mask OR register (R/W: 0320h) . . . 53 8.4.6 ISO IRQ Mask AND register (R/W: 0324h) . . 54 8.4.7 INT IRQ Mask AND register (R/W: 0328h) . . 54 8.4.8 ATL IRQ Mask AND register (R/W: 032Ch) . . 54 9 Philips Transfer Descriptor. . . . . . . . . . . . . . . 55 9.1 High-speed bulk IN and OUT, Queue Head Asynchronous (QHA) (patent-pending) . . . . . 58 9.2 High-speed isochronous IN and OUT, isochronous Transfer Descriptor (iTD) (patent-pending). . . . . . . . . . . . . . . . . . . . . . . 62 9.3 High-speed interrupt IN and OUT, Queue Head Periodic (QHP) (patent-pending) . . . . . . . . . . 66 9.4 Start and complete split for bulk, Queue Head Asynchronous Start Split and Start Complete (QHA-SS/SC) (patent-pending) . . . . . . . . . . . 70 9.5 Start and complete split for isochronous, Split isochronous Transfer Descriptor (SiTD) (patent-pending). . . . . . . . . . . . . . . . . . . . . . . 74 9.6 Start and complete split for interrupt (patent-pending). . . . . . . . . . . . . . . . . . . . . . . 78 10 Power consumption . . . . . . . . . . . . . . . . . . . . 82 11 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 83
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Product data sheet
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Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
12 13 14 14.1 14.1.1 14.1.2 14.1.3 14.2 14.2.1 14.2.2 14.2.3 14.2.4 15 16 16.1 16.2 16.3 16.4 16.5 17 18 19 20 21 22 23 24
Recommended operating conditions. . . . . . . 83 Static characteristics. . . . . . . . . . . . . . . . . . . . 84 Dynamic characteristics . . . . . . . . . . . . . . . . . 86 PIO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Register or memory write . . . . . . . . . . . . . . . . 88 Register read . . . . . . . . . . . . . . . . . . . . . . . . . 89 Memory read . . . . . . . . . . . . . . . . . . . . . . . . . 90 DMA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Single cycle: DMA read . . . . . . . . . . . . . . . . . 91 Single cycle: DMA write . . . . . . . . . . . . . . . . . 92 Multicycle: DMA read . . . . . . . . . . . . . . . . . . . 93 Multicycle: DMA write . . . . . . . . . . . . . . . . . . . 94 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 95 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 96 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 96 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 97 Package related soldering information . . . . . . 97 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 98 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 99 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 100 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Contact information . . . . . . . . . . . . . . . . . . . 100
(c) Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 8 November 2004 Document number: 9397 750 13257
Published in The Netherlands

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